[llvm] d90468d - [CSKY] Add support for half-precision floats
Zi Xuan Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 00:03:26 PDT 2023
Author: Zi Xuan Wu (Zeson)
Date: 2023-06-14T15:03:07+08:00
New Revision: d90468d1619634f0629c7637d25716956ccc6b7a
URL: https://github.com/llvm/llvm-project/commit/d90468d1619634f0629c7637d25716956ccc6b7a
DIFF: https://github.com/llvm/llvm-project/commit/d90468d1619634f0629c7637d25716956ccc6b7a.diff
LOG: [CSKY] Add support for half-precision floats
Complete fp16 support by ensuring that load extension / truncate store operations are properly expanded.
Added:
llvm/test/CodeGen/CSKY/fpu/fp16-promote.ll
Modified:
llvm/lib/Target/CSKY/CSKYISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index bd13e20166d07..2c8649a3b6ad1 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -117,7 +117,8 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
};
ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
- ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN};
+ ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN,
+ ISD::FP16_TO_FP, ISD::FP_TO_FP16};
if (STI.useHardFloat()) {
@@ -136,10 +137,14 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
+ setTruncStoreAction(MVT::f32, MVT::f16, Expand);
}
if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f16, Expand);
}
}
diff --git a/llvm/test/CodeGen/CSKY/fpu/fp16-promote.ll b/llvm/test/CodeGen/CSKY/fpu/fp16-promote.ll
new file mode 100644
index 0000000000000..7877343ffa74f
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/fp16-promote.ll
@@ -0,0 +1,312 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf,+fpuv2_df | FileCheck %s --check-prefix=CHECK-FPUV2
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf,+fpuv3_df | FileCheck %s --check-prefix=CHECK-FPUV3
+
+define void @test_load_store(ptr %p, ptr %q) nounwind {
+; CHECK-FPUV2-LABEL: test_load_store:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV2-NEXT: st16.h a0, (a1, 0)
+; CHECK-FPUV2-NEXT: rts16
+;
+; CHECK-FPUV3-LABEL: test_load_store:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV3-NEXT: st16.h a0, (a1, 0)
+; CHECK-FPUV3-NEXT: rts16
+ %a = load half, ptr %p
+ store half %a, ptr %q
+ ret void
+}
+
+define float @test_fpextend_float(ptr %p) nounwind {
+; CHECK-FPUV2-LABEL: test_fpextend_float:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 4
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI1_0]
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 4
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI1_0:
+; CHECK-FPUV2-NEXT: .long __gnu_h2f_ieee
+;
+; CHECK-FPUV3-LABEL: test_fpextend_float:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 4
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI1_0]
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 4
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI1_0:
+; CHECK-FPUV3-NEXT: .long __gnu_h2f_ieee
+ %a = load half, ptr %p
+ %r = fpext half %a to float
+ ret float %r
+}
+
+define double @test_fpextend_double(ptr %p) nounwind {
+; CHECK-FPUV2-LABEL: test_fpextend_double:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 4
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI2_0]
+; CHECK-FPUV2-NEXT: fstod vr0, vr0
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 4
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI2_0:
+; CHECK-FPUV2-NEXT: .long __gnu_h2f_ieee
+;
+; CHECK-FPUV3-LABEL: test_fpextend_double:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 4
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI2_0]
+; CHECK-FPUV3-NEXT: fstod vr0, vr0
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 4
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI2_0:
+; CHECK-FPUV3-NEXT: .long __gnu_h2f_ieee
+ %a = load half, ptr %p
+ %r = fpext half %a to double
+ ret double %r
+}
+
+define void @test_fptrunc_float(float %f, ptr %p) nounwind {
+; CHECK-FPUV2-LABEL: test_fptrunc_float:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 8
+; CHECK-FPUV2-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: mov16 l0, a0
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI3_0]
+; CHECK-FPUV2-NEXT: st16.h a0, (l0, 0)
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 8
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI3_0:
+; CHECK-FPUV2-NEXT: .long __gnu_f2h_ieee
+;
+; CHECK-FPUV3-LABEL: test_fptrunc_float:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 8
+; CHECK-FPUV3-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: mov16 l0, a0
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI3_0]
+; CHECK-FPUV3-NEXT: st16.h a0, (l0, 0)
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 8
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI3_0:
+; CHECK-FPUV3-NEXT: .long __gnu_f2h_ieee
+ %a = fptrunc float %f to half
+ store half %a, ptr %p
+ ret void
+}
+
+define void @test_fptrunc_double(double %d, ptr %p) nounwind {
+; CHECK-FPUV2-LABEL: test_fptrunc_double:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 8
+; CHECK-FPUV2-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: mov16 l0, a0
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI4_0]
+; CHECK-FPUV2-NEXT: st16.h a0, (l0, 0)
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 8
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI4_0:
+; CHECK-FPUV2-NEXT: .long __truncdfhf2
+;
+; CHECK-FPUV3-LABEL: test_fptrunc_double:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 8
+; CHECK-FPUV3-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: mov16 l0, a0
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI4_0]
+; CHECK-FPUV3-NEXT: st16.h a0, (l0, 0)
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 8
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI4_0:
+; CHECK-FPUV3-NEXT: .long __truncdfhf2
+ %a = fptrunc double %d to half
+ store half %a, ptr %p
+ ret void
+}
+
+define void @test_fadd(ptr %p, ptr %q) nounwind {
+; CHECK-FPUV2-LABEL: test_fadd:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 20
+; CHECK-FPUV2-NEXT: fstd vr8, (sp, 12) # 8-byte Folded Spill
+; CHECK-FPUV2-NEXT: st16.w l1, (sp, 8) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: mov16 l0, a1
+; CHECK-FPUV2-NEXT: mov16 l1, a0
+; CHECK-FPUV2-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI5_0]
+; CHECK-FPUV2-NEXT: fmovs vr8, vr0
+; CHECK-FPUV2-NEXT: ld16.h a0, (l0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI5_0]
+; CHECK-FPUV2-NEXT: fadds vr0, vr8, vr0
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI5_1]
+; CHECK-FPUV2-NEXT: st16.h a0, (l1, 0)
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: fldd vr8, (sp, 12) # 8-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 20
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI5_0:
+; CHECK-FPUV2-NEXT: .long __gnu_h2f_ieee
+; CHECK-FPUV2-NEXT: .LCPI5_1:
+; CHECK-FPUV2-NEXT: .long __gnu_f2h_ieee
+;
+; CHECK-FPUV3-LABEL: test_fadd:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 20
+; CHECK-FPUV3-NEXT: fst.64 vr8, (sp, 12) # 8-byte Folded Spill
+; CHECK-FPUV3-NEXT: st16.w l1, (sp, 8) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: mov16 l0, a1
+; CHECK-FPUV3-NEXT: mov16 l1, a0
+; CHECK-FPUV3-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI5_0]
+; CHECK-FPUV3-NEXT: fmov.32 vr8, vr0
+; CHECK-FPUV3-NEXT: ld16.h a0, (l0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI5_0]
+; CHECK-FPUV3-NEXT: fadd.32 vr0, vr8, vr0
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI5_1]
+; CHECK-FPUV3-NEXT: st16.h a0, (l1, 0)
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: fld.64 vr8, (sp, 12) # 8-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 20
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI5_0:
+; CHECK-FPUV3-NEXT: .long __gnu_h2f_ieee
+; CHECK-FPUV3-NEXT: .LCPI5_1:
+; CHECK-FPUV3-NEXT: .long __gnu_f2h_ieee
+ %a = load half, ptr %p
+ %b = load half, ptr %q
+ %r = fadd half %a, %b
+ store half %r, ptr %p
+ ret void
+}
+
+define void @test_fmul(ptr %p, ptr %q) nounwind {
+; CHECK-FPUV2-LABEL: test_fmul:
+; CHECK-FPUV2: # %bb.0:
+; CHECK-FPUV2-NEXT: subi16 sp, sp, 20
+; CHECK-FPUV2-NEXT: fstd vr8, (sp, 12) # 8-byte Folded Spill
+; CHECK-FPUV2-NEXT: st16.w l1, (sp, 8) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV2-NEXT: mov16 l0, a1
+; CHECK-FPUV2-NEXT: mov16 l1, a0
+; CHECK-FPUV2-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI6_0]
+; CHECK-FPUV2-NEXT: fmovs vr8, vr0
+; CHECK-FPUV2-NEXT: ld16.h a0, (l0, 0)
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI6_0]
+; CHECK-FPUV2-NEXT: fmuls vr0, vr8, vr0
+; CHECK-FPUV2-NEXT: jsri32 [.LCPI6_1]
+; CHECK-FPUV2-NEXT: st16.h a0, (l1, 0)
+; CHECK-FPUV2-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload
+; CHECK-FPUV2-NEXT: fldd vr8, (sp, 12) # 8-byte Folded Reload
+; CHECK-FPUV2-NEXT: addi16 sp, sp, 20
+; CHECK-FPUV2-NEXT: rts16
+; CHECK-FPUV2-NEXT: .p2align 1
+; CHECK-FPUV2-NEXT: # %bb.1:
+; CHECK-FPUV2-NEXT: .p2align 2, 0x0
+; CHECK-FPUV2-NEXT: .LCPI6_0:
+; CHECK-FPUV2-NEXT: .long __gnu_h2f_ieee
+; CHECK-FPUV2-NEXT: .LCPI6_1:
+; CHECK-FPUV2-NEXT: .long __gnu_f2h_ieee
+;
+; CHECK-FPUV3-LABEL: test_fmul:
+; CHECK-FPUV3: # %bb.0:
+; CHECK-FPUV3-NEXT: subi16 sp, sp, 20
+; CHECK-FPUV3-NEXT: fst.64 vr8, (sp, 12) # 8-byte Folded Spill
+; CHECK-FPUV3-NEXT: st16.w l1, (sp, 8) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st16.w l0, (sp, 4) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
+; CHECK-FPUV3-NEXT: mov16 l0, a1
+; CHECK-FPUV3-NEXT: mov16 l1, a0
+; CHECK-FPUV3-NEXT: ld16.h a0, (a0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI6_0]
+; CHECK-FPUV3-NEXT: fmov.32 vr8, vr0
+; CHECK-FPUV3-NEXT: ld16.h a0, (l0, 0)
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI6_0]
+; CHECK-FPUV3-NEXT: fmul.32 vr0, vr8, vr0
+; CHECK-FPUV3-NEXT: jsri32 [.LCPI6_1]
+; CHECK-FPUV3-NEXT: st16.h a0, (l1, 0)
+; CHECK-FPUV3-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload
+; CHECK-FPUV3-NEXT: fld.64 vr8, (sp, 12) # 8-byte Folded Reload
+; CHECK-FPUV3-NEXT: addi16 sp, sp, 20
+; CHECK-FPUV3-NEXT: rts16
+; CHECK-FPUV3-NEXT: .p2align 1
+; CHECK-FPUV3-NEXT: # %bb.1:
+; CHECK-FPUV3-NEXT: .p2align 2, 0x0
+; CHECK-FPUV3-NEXT: .LCPI6_0:
+; CHECK-FPUV3-NEXT: .long __gnu_h2f_ieee
+; CHECK-FPUV3-NEXT: .LCPI6_1:
+; CHECK-FPUV3-NEXT: .long __gnu_f2h_ieee
+ %a = load half, ptr %p
+ %b = load half, ptr %q
+ %r = fmul half %a, %b
+ store half %r, ptr %p
+ ret void
+}
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