[PATCH] D152854: [SelectionDAG][RISCV] Add very basic PromoteIntegerOp support for VP_SIGN/ZERO_EXTEND.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 13:34:12 PDT 2023
craig.topper created this revision.
craig.topper added reviewers: reames, frasercrmck, rogfer01, fakepaper56.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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We don't have VP_ANY_EXTEND or VP_SIGN_EXTEND_INREG yet so I've
deviated a little from the non-VP lowering.
My goal was to fix the crashes that occurs on these test cases without this patch.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D152854
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
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