[llvm] a5cd198 - [SelectionDAG] Don't allow type legalization to create noop VP_TRUNCATE.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 12:51:54 PDT 2023
Author: Craig Topper
Date: 2023-06-13T12:51:24-07:00
New Revision: a5cd198181f937417c988e82f50461adb29aef76
URL: https://github.com/llvm/llvm-project/commit/a5cd198181f937417c988e82f50461adb29aef76
DIFF: https://github.com/llvm/llvm-project/commit/a5cd198181f937417c988e82f50461adb29aef76.diff
LOG: [SelectionDAG] Don't allow type legalization to create noop VP_TRUNCATE.
Type legalization may need to promote the result to the same type
as the input. Instead of forming a vp_truncate with the same
source and dest type, don't create any vp_truncate.
Handling in getNode like is done for ISD::TRUNCATE.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c9d15fc0e40c7..c947293593e47 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6922,6 +6922,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (N1.getValueType() == VT)
return N1;
break;
+ case ISD::VP_TRUNCATE:
+ // Don't create noop vp_truncate.
+ if (N1.getValueType() == VT)
+ return N1;
+ break;
}
// Memoize node if it doesn't produce a flag.
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
index f628ac94859f3..a5f61ca5838a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
@@ -512,3 +512,13 @@ define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext
%v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)
ret <32 x i32> %v
}
+
+declare <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8>, <2 x i1>, i32)
+
+define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {
+; CHECK-LABEL: vtrunc_v2i7_v2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)
+ ret <2 x i7> %v
+}
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