[llvm] 894d047 - [RISCV] Remove RISCVII::hasMergeOp. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 10:54:11 PDT 2023
Author: Craig Topper
Date: 2023-06-13T10:54:00-07:00
New Revision: 894d047056a684da8b993ca4aa1bd82eddeb0113
URL: https://github.com/llvm/llvm-project/commit/894d047056a684da8b993ca4aa1bd82eddeb0113
DIFF: https://github.com/llvm/llvm-project/commit/894d047056a684da8b993ca4aa1bd82eddeb0113.diff
LOG: [RISCV] Remove RISCVII::hasMergeOp. NFC
We can mostly get this from the operand info in MCInstrDesc.
The exception is the _TIED pseudos so I've added a new flag for those.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D152313
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 0715dc4f9c194..a481bc50205b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -58,7 +58,7 @@ enum {
ConstraintShift = InstFormatShift + 5,
VS2Constraint = 0b001 << ConstraintShift,
VS1Constraint = 0b010 << ConstraintShift,
- VMConstraint = 0b100 << ConstraintShift,
+ VMConstraint = 0b100 << ConstraintShift,
ConstraintMask = 0b111 << ConstraintShift,
VLMulShift = ConstraintShift + 3,
@@ -68,15 +68,14 @@ enum {
ForceTailAgnosticShift = VLMulShift + 3,
ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
- // Does this instruction have a merge operand that must be removed when
- // converting to MCInst. It will be the first explicit use operand. Used by
- // RVV Pseudos.
- HasMergeOpShift = ForceTailAgnosticShift + 1,
- HasMergeOpMask = 1 << HasMergeOpShift,
+ // Is this a _TIED vector pseudo instruction. For these instructions we
+ // shouldn't skip the tied operand when converting to MC instructions.
+ IsTiedPseudoShift = ForceTailAgnosticShift + 1,
+ IsTiedPseudoMask = 1 << IsTiedPseudoShift,
// Does this instruction have a SEW operand. It will be the last explicit
// operand unless there is a vector policy operand. Used by RVV Pseudos.
- HasSEWOpShift = HasMergeOpShift + 1,
+ HasSEWOpShift = IsTiedPseudoShift + 1,
HasSEWOpMask = 1 << HasSEWOpShift,
// Does this instruction have a VL operand. It will be the second to last
@@ -140,9 +139,9 @@ static inline VLMUL getLMul(uint64_t TSFlags) {
static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
return TSFlags & ForceTailAgnosticMask;
}
-/// \returns true if there is a merge operand for the instruction.
-static inline bool hasMergeOp(uint64_t TSFlags) {
- return TSFlags & HasMergeOpMask;
+/// \returns true if this a _TIED pseudo.
+static inline bool isTiedPseudo(uint64_t TSFlags) {
+ return TSFlags & IsTiedPseudoMask;
}
/// \returns true if there is a SEW operand for the instruction.
static inline bool hasSEWOp(uint64_t TSFlags) {
@@ -165,12 +164,6 @@ static inline bool usesMaskPolicy(uint64_t TSFlags) {
return TSFlags & UsesMaskPolicyMask;
}
-static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
- assert(hasMergeOp(Desc.TSFlags));
- assert(!Desc.isVariadic());
- return Desc.getNumDefs();
-}
-
static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
const uint64_t TSFlags = Desc.TSFlags;
// This method is only called if we expect to have a VL operand, and all
@@ -199,9 +192,7 @@ static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
// Is the first def operand tied to the first use operand. This is true for
// vector pseudo instructions that have a merge operand for tail/mask
// undisturbed. It's also true for vector FMA instructions where one of the
-// operands is also the destination register. This is
diff erent than
-// RISCVII::hasMergeOp which only indicates whether the tied operand from the
-// pseudoinstruction also exists on the MC layer instruction.
+// operands is also the destination register.
static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
return Desc.getNumDefs() < Desc.getNumOperands() &&
Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 4d9fc4bc4c87c..ee2746b4cd055 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -631,10 +631,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
assert(MF && "MBB expected to be in a machine function");
const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+ const TargetInstrInfo *TII = Subtarget.getInstrInfo();
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
assert(TRI && "TargetRegisterInfo expected");
- uint64_t TSFlags = MI->getDesc().TSFlags;
+ const MCInstrDesc &MCID = MI->getDesc();
+ uint64_t TSFlags = MCID.TSFlags;
unsigned NumOps = MI->getNumExplicitOperands();
// Skip policy, VL and SEW operands which are the last operands if present.
@@ -652,10 +654,17 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
if (hasVLOutput && OpNo == 1)
continue;
- // Skip merge op. It should be the first operand after the result.
- if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
- assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
- continue;
+ // Skip merge op. It should be the first operand after the defs.
+ if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
+ assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
+ "Expected tied to first def.");
+ const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
+ // Skip if the next operand in OutMI is not supposed to be tied. Unless it
+ // is a _TIED instruction.
+ if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) <
+ 0 &&
+ !RISCVII::isTiedPseudo(TSFlags))
+ continue;
}
MCOperand MCOp;
@@ -704,7 +713,6 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
// Unmasked pseudo instructions need to append dummy mask operand to
// V instructions. All V instructions are modeled as the masked version.
- const TargetInstrInfo *TII = Subtarget.getInstrInfo();
const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 1e00808773063..509f90ac82437 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -190,8 +190,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
bit ForceTailAgnostic = false;
let TSFlags{11} = ForceTailAgnostic;
- bit HasMergeOp = 0;
- let TSFlags{12} = HasMergeOp;
+ bit IsTiedPseudo = 0;
+ let TSFlags{12} = IsTiedPseudo;
bit HasSEWOp = 0;
let TSFlags{13} = HasSEWOp;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e1399b137aba1..e3f7d9785542e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1793,13 +1793,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
}
const uint64_t TSFlags = Desc.TSFlags;
- if (RISCVII::hasMergeOp(TSFlags)) {
- unsigned OpIdx = RISCVII::getMergeOpNum(Desc);
- if (MI.findTiedOperandIdx(0) != OpIdx) {
- ErrInfo = "Merge op improperly tied";
- return false;
- }
- }
if (RISCVII::hasVLOp(TSFlags)) {
const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
if (!Op.isImm() && !Op.isReg()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 5028fa4b5ee2b..261b068035890 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -707,7 +707,6 @@ class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -724,7 +723,6 @@ class VPseudoUSLoadMask<VReg RetClass, int EEW> :
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -751,7 +749,6 @@ class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -768,7 +765,6 @@ class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -795,7 +791,6 @@ class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -812,7 +807,6 @@ class VPseudoSLoadMask<VReg RetClass, int EEW>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -844,7 +838,6 @@ class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
}
@@ -862,7 +855,6 @@ class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -936,7 +928,6 @@ class VPseudoNullaryNoMaskTU<VReg RegClass>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoNullaryMask<VReg RegClass>:
@@ -949,7 +940,6 @@ class VPseudoNullaryMask<VReg RegClass>:
let Constraints ="$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let UsesMaskPolicy = 1;
let HasVecPolicyOp = 1;
}
@@ -995,7 +985,6 @@ class VPseudoUnaryNoMaskTU<DAGOperand RetClass, DAGOperand OpClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
@@ -1009,7 +998,6 @@ class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1024,7 +1012,6 @@ class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1039,7 +1026,6 @@ class VPseudoUnaryMaskTA_NoExcept<VReg RetClass, VReg OpClass, string Constraint
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
let usesCustomInserter = 1;
@@ -1055,7 +1041,6 @@ class VPseudoUnaryMaskTA_FRM<VReg RetClass, VReg OpClass, string Constraint = ""
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
let usesCustomInserter = 1;
@@ -1088,7 +1073,6 @@ class VPseudoUnaryAnyMask<VReg RetClass,
let Constraints = "@earlyclobber $rd, $rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoBinaryNoMask<VReg RetClass,
@@ -1119,7 +1103,6 @@ class VPseudoBinaryNoMaskTU<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
// Special version of VPseudoBinaryNoMask where we pretend the first source is
@@ -1140,6 +1123,7 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
let isConvertibleToThreeAddress = 1;
+ let IsTiedPseudo = 1;
}
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1183,7 +1167,6 @@ class VPseudoBinaryMask<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoBinaryMaskPolicy<VReg RetClass,
@@ -1201,7 +1184,6 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1221,7 +1203,6 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
}
@@ -1241,7 +1222,6 @@ class VPseudoBinaryMOutMask<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1262,9 +1242,9 @@ class VPseudoTiedBinaryMask<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 0; // Merge is also rs2.
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
+ let IsTiedPseudo = 1;
}
class VPseudoBinaryCarryIn<VReg RetClass,
@@ -1285,7 +1265,6 @@ class VPseudoBinaryCarryIn<VReg RetClass,
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 0;
let VLMul = MInfo.value;
}
@@ -1307,7 +1286,6 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 0;
let VLMul = MInfo.value;
}
@@ -1327,7 +1305,6 @@ class VPseudoTernaryNoMask<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
@@ -1346,7 +1323,6 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
let HasVecPolicyOp = 1;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1371,7 +1347,6 @@ class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -1387,7 +1362,6 @@ class VPseudoUSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1414,7 +1388,6 @@ class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -1430,7 +1403,6 @@ class VPseudoUSSegLoadFFMask<VReg RetClass, int EEW, bits<4> NF>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1457,7 +1429,6 @@ class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let Constraints = "$rd = $merge";
}
@@ -1474,7 +1445,6 @@ class VPseudoSSegLoadMask<VReg RetClass, int EEW, bits<4> NF>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
@@ -1509,7 +1479,6 @@ class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMU
let Constraints = "@earlyclobber $rd, $rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
}
class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1528,7 +1497,6 @@ class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let Constraints = "@earlyclobber $rd, $rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
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