[PATCH] D152790: [ARM] Fix codegen of unaligned volatile load/store of i64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:10085
+      LD->getAlign() >= (Subtarget->hasV6Ops()
+                             ? DAG.getDataLayout().getABITypeAlign(
+                                   Type::getInt64Ty(*DAG.getContext()))
----------------
Using getABITypeAlign() like this is confusing; if you mean "4", just write 4.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152790/new/

https://reviews.llvm.org/D152790