[llvm] 445ec58 - [RISCV] Add support for llvm.prefetch to use Zicbop instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-13T09:51:30-07:00
New Revision: 445ec58f5fe304112db8c1105ba6814a7aea2161

URL: https://github.com/llvm/llvm-project/commit/445ec58f5fe304112db8c1105ba6814a7aea2161
DIFF: https://github.com/llvm/llvm-project/commit/445ec58f5fe304112db8c1105ba6814a7aea2161.diff

LOG: [RISCV] Add support for llvm.prefetch to use Zicbop instructions.

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D152723

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
    llvm/test/CodeGen/RISCV/prefetch.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3dc25cf43cf0c..57ec652d446d5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -501,6 +501,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.is64Bit())
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
 
+  if (Subtarget.hasStdExtZicbop()) {
+    setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
+  }
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index 8cd1fc4cf1eda..509d1cfcd8744 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -42,7 +42,7 @@ class CBO_r<bits<12> optype, string opcodestr>
   let rd = 0b00000;
 }
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 class Prefetch_ri<bits<5> optype, string opcodestr>
     : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPR:$rs1, simm12_lsb00000:$imm12),
               opcodestr, "${imm12}(${rs1})"> {
@@ -69,3 +69,17 @@ def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
 def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
 def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
 } // Predicates = [HasStdExtZicbop]
+
+//===----------------------------------------------------------------------===//
+// Patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicbop] in {
+  // FIXME: Match address with offset
+  def : Pat<(prefetch GPR:$rs1, imm, imm, (XLenVT 0)),
+            (PREFETCH_I GPR:$rs1, 0)>;
+  def : Pat<(prefetch GPR:$rs1, (XLenVT 0), imm, (XLenVT 1)),
+            (PREFETCH_R GPR:$rs1, 0)>;
+  def : Pat<(prefetch GPR:$rs1, (XLenVT 1), imm, (XLenVT 1)),
+            (PREFETCH_W GPR:$rs1, 0)>;
+}

diff  --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index 1c8861dbd8585..114e9df862327 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -3,17 +3,75 @@
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=zicbop -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64ZICBOP %s
 
 declare void @llvm.prefetch(ptr, i32, i32, i32)
 
-define void @test_prefetch(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch:
+define void @test_prefetch_read(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_read:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
-; RV64I-LABEL: test_prefetch:
+; RV64I-LABEL: test_prefetch_read:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_read:
+; RV32ZICBOP:       # %bb.0:
+; RV32ZICBOP-NEXT:    prefetch.r 0(a0)
+; RV32ZICBOP-NEXT:    ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_read:
+; RV64ZICBOP:       # %bb.0:
+; RV64ZICBOP-NEXT:    prefetch.r 0(a0)
+; RV64ZICBOP-NEXT:    ret
   call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 1)
   ret void
 }
+
+define void @test_prefetch_write(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_write:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_prefetch_write:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_write:
+; RV32ZICBOP:       # %bb.0:
+; RV32ZICBOP-NEXT:    prefetch.w 0(a0)
+; RV32ZICBOP-NEXT:    ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_write:
+; RV64ZICBOP:       # %bb.0:
+; RV64ZICBOP-NEXT:    prefetch.w 0(a0)
+; RV64ZICBOP-NEXT:    ret
+  call void @llvm.prefetch(ptr %a, i32 1, i32 2, i32 1)
+  ret void
+}
+
+define void @test_prefetch_instruction(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_instruction:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test_prefetch_instruction:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_instruction:
+; RV32ZICBOP:       # %bb.0:
+; RV32ZICBOP-NEXT:    prefetch.i 0(a0)
+; RV32ZICBOP-NEXT:    ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_instruction:
+; RV64ZICBOP:       # %bb.0:
+; RV64ZICBOP-NEXT:    prefetch.i 0(a0)
+; RV64ZICBOP-NEXT:    ret
+  call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 0)
+  ret void
+}