[PATCH] D152821: [RISCV] Add support for Xcvmac extension in CV32E40P

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Implement Xcvmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152821

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td
  llvm/test/MC/RISCV/corev/mac/invalid.s
  llvm/test/MC/RISCV/corev/mac/mac-invalid.s
  llvm/test/MC/RISCV/corev/mac/mac.s
  llvm/test/MC/RISCV/corev/mac/machhsn-invalid.s
  llvm/test/MC/RISCV/corev/mac/machhsn.s
  llvm/test/MC/RISCV/corev/mac/machhsrn-invalid.s
  llvm/test/MC/RISCV/corev/mac/machhsrn.s
  llvm/test/MC/RISCV/corev/mac/machhun-invalid.s
  llvm/test/MC/RISCV/corev/mac/machhun.s
  llvm/test/MC/RISCV/corev/mac/machhurn-invalid.s
  llvm/test/MC/RISCV/corev/mac/machhurn.s
  llvm/test/MC/RISCV/corev/mac/macsn-invalid.s
  llvm/test/MC/RISCV/corev/mac/macsn.s
  llvm/test/MC/RISCV/corev/mac/macsrn-invalid.s
  llvm/test/MC/RISCV/corev/mac/macsrn.s
  llvm/test/MC/RISCV/corev/mac/macun-invalid.s
  llvm/test/MC/RISCV/corev/mac/macun.s
  llvm/test/MC/RISCV/corev/mac/macurn-invalid.s
  llvm/test/MC/RISCV/corev/mac/macurn.s
  llvm/test/MC/RISCV/corev/mac/msu-invalid.s
  llvm/test/MC/RISCV/corev/mac/msu.s
  llvm/test/MC/RISCV/corev/mac/mulhhs-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhs.s
  llvm/test/MC/RISCV/corev/mac/mulhhsn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhsn.s
  llvm/test/MC/RISCV/corev/mac/mulhhsrn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhsrn.s
  llvm/test/MC/RISCV/corev/mac/mulhhu-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhu.s
  llvm/test/MC/RISCV/corev/mac/mulhhun-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhun.s
  llvm/test/MC/RISCV/corev/mac/mulhhurn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulhhurn.s
  llvm/test/MC/RISCV/corev/mac/muls-invalid.s
  llvm/test/MC/RISCV/corev/mac/muls.s
  llvm/test/MC/RISCV/corev/mac/mulsn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulsn.s
  llvm/test/MC/RISCV/corev/mac/mulsrn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulsrn.s
  llvm/test/MC/RISCV/corev/mac/mulu-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulu.s
  llvm/test/MC/RISCV/corev/mac/mulun-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulun.s
  llvm/test/MC/RISCV/corev/mac/mulurn-invalid.s
  llvm/test/MC/RISCV/corev/mac/mulurn.s

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