[PATCH] D152688: [Aarch64] Add Cortex-A510 specific scheduling

Ricardo Jesus via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 13 08:00:46 PDT 2023


rjj added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:645-646
+// Arithmetic, basic
+def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>],
+             (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^(ADD|SUB)_ZZZ_[BHSD]$",
----------------
I think there are not as many UNDEF patterns as the ones matched here (in other words the regex could be tightened a bit). UNDEF patterns only seem to only exist for `ABS|CNOT|NEG`.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:653
+                        "^SADDLBT_ZZZ_[HSD]$",
+                        "^[SU]H(ADD|SUB|SUBR)_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^SSUBL(BT|TB)_ZZZ_[HSD]$")>;
----------------
I don't think these UNDEFs exist.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:659
+             (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]$",
+                        "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]$",
----------------
No UNDEFs for `ADD|SUB|SUBR`.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:662
+                        "^[SU]Q(ADD|SUB)_ZI_[BHSD]$",
+                        "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^(UQSUB|UQSUBR)_ZPmZ_(UNDEF_)?[BHSD]$")>;
----------------
These UNDEFs don't seem to exist.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:663
+                        "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^(UQSUB|UQSUBR)_ZPmZ_(UNDEF_)?[BHSD]$")>;
+
----------------
Same as above.

There are a few other places where the UNDEF patterns don't seem to exist, but before going through them, any reason why you've included these extra UNDEFs here?


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:1101
+// Floating point reduction, F32
+// REVISIT
+def : InstRW<[CortexA510MCWrite<12, 11, CortexA510UnitVALU0>],
----------------
Straggling comment?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152688/new/

https://reviews.llvm.org/D152688



More information about the llvm-commits mailing list