[llvm] dbbd627 - [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions

Venkata Ramanaiah Nalamothu via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 13 07:48:16 PDT 2023 

Author: Venkata Ramanaiah Nalamothu
Date: 2023-06-13T20:18:08+05:30
New Revision: dbbd6276f20aa8bcf472f12a16a5a895ff797313

URL: https://github.com/llvm/llvm-project/commit/dbbd6276f20aa8bcf472f12a16a5a895ff797313
DIFF: https://github.com/llvm/llvm-project/commit/dbbd6276f20aa8bcf472f12a16a5a895ff797313.diff

LOG: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions

Currently `llvm/test/MC/RISCV/rv64zbb-valid.s` doesn't cover all
the instructions e.g. `maxu` and `llvm/test/MC/RISCV/rv32zbb-valid.s`
can have rv64 run lines, similar to what Zba instruction tests have.

This patch does the following.
- Add rv64 run lines in `llvm/test/MC/RISCV/rv32zbb-valid.s`
- Keep only rv64 specific instructions in `llvm/test/MC/RISCV/rv64zbb-valid.s`
- Move rv32 instructions, with different encodings from rv64, into
  `llvm/test/MC/RISCV/rv32zbb-only-valid.s`

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D152680

Added: 
    

Modified: 
    llvm/test/MC/RISCV/rv32zbb-only-valid.s
    llvm/test/MC/RISCV/rv32zbb-valid.s
    llvm/test/MC/RISCV/rv64zbb-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/RISCV/rv32zbb-only-valid.s b/llvm/test/MC/RISCV/rv32zbb-only-valid.s
index 13afa20cde4ae..3668b13fc22f4 100644
--- a/llvm/test/MC/RISCV/rv32zbb-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-only-valid.s
@@ -8,6 +8,12 @@
 # CHECK-ASM-AND-OBJ: zext.h t0, t1
 # CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
 zext.h t0, t1
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
 # CHECK-ASM-AND-OBJ: rev8 t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
 rev8 t0, t1

diff  --git a/llvm/test/MC/RISCV/rv32zbb-valid.s b/llvm/test/MC/RISCV/rv32zbb-valid.s
index b9eef05c7e43d..2e5b9cce39509 100644
--- a/llvm/test/MC/RISCV/rv32zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbb-valid.s
@@ -1,9 +1,14 @@
 # With Bitmanip base extension:
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \
 # RUN:     | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \
+# RUN:     | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: clz t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
@@ -21,9 +26,6 @@ sext.b t0, t1
 # CHECK-ASM-AND-OBJ: sext.h t0, t1
 # CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
 sext.h t0, t1
-# CHECK-ASM-AND-OBJ: zext.h t0, t1
-# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
-zext.h t0, t1
 
 # CHECK-ASM-AND-OBJ: min t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
@@ -53,12 +55,6 @@ rol t0, t1, t2
 # CHECK-ASM-AND-OBJ: ror t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
 ror t0, t1, t2
-# CHECK-ASM-AND-OBJ: rori t0, t1, 31
-# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
-rori t0, t1, 31
-# CHECK-ASM-AND-OBJ: rori t0, t1, 0
-# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
-rori t0, t1, 0
 # CHECK-ASM-AND-OBJ: orc.b t0, t1
 # CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
 orc.b t0, t1

diff  --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
index 16ec53aec17d6..ac7070af1aec2 100644
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -5,34 +5,18 @@
 # RUN:     | llvm-objdump --mattr=+zbb -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: clz t0, t1
-# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
-clz t0, t1
-# CHECK-ASM-AND-OBJ: ctz t0, t1
-# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
-ctz t0, t1
-# CHECK-ASM-AND-OBJ: cpop t0, t1
-# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
-cpop t0, t1
-# CHECK-ASM-AND-OBJ: min t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
-min t0, t1, t2
-# CHECK-ASM-AND-OBJ: minu t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
-minu t0, t1, t2
-# CHECK-ASM-AND-OBJ: max t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
-max t0, t1, t2
-
-# CHECK-ASM-AND-OBJ: sext.b t0, t1
-# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
-sext.b t0, t1
-# CHECK-ASM-AND-OBJ: sext.h t0, t1
-# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
-sext.h t0, t1
 # CHECK-ASM-AND-OBJ: zext.h t0, t1
 # CHECK-ASM: encoding: [0xbb,0x42,0x03,0x08]
 zext.h t0, t1
+# CHECK-ASM-AND-OBJ: rori t0, t1, 63
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x63]
+rori t0, t1, 63
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
+# CHECK-ASM-AND-OBJ: rev8 t0, t1
+# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
+rev8 t0, t1
 
 # CHECK-ASM-AND-OBJ: clzw t0, t1
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
@@ -66,6 +50,3 @@ roriw t0, t1, 31
 # CHECK-ASM-AND-OBJ: roriw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
 roriw t0, t1, 0
-# CHECK-ASM-AND-OBJ: rev8 t0, t1
-# CHECK-ASM: encoding: [0x93,0x52,0x83,0x6b]
-rev8 t0, t1

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