[PATCH] D151894: [AArch64] Neoverse V2 scheduling model

[Ricardo Jesus via Phabricator via llvm-commits]

rjj added a comment.

In D151894#4402483 <https://reviews.llvm.org/D151894#4402483>, @SjoerdMeijer wrote:

> It is probably good to double check performance numbers after these (small) modifications.

As of the last revision, performance on SPEC2017 INT and FP is comparable to that obtained with the N2 model.

In D151894#4402776 <https://reviews.llvm.org/D151894#4402776>, @dmgreen wrote:

> Harvin has been looking at writing Cortex-A510 scheduling model recently, and noticed that most of the SVE instructions use Pseudos through a lot of the pipeline instead of the real instructions. Like ABS_ZPmZ_UNDEF_B and ADDHA_MPPZ_D_PSEUDO_D. You may find that especially in pre-ra scheduling the instruction do not match the real ones added here, and they need extra regex's to match the pseudos. (The same is likely true of the Neoverse-N2 scheduling model).

Thanks for the heads up, the UNDEFs should now be getting matched. I'm not sure how this could be tested though, do you have any ideas?


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