[PATCH] D152810: [RISCV] Fix IMPLICIT_DEF check in doPeepholeMaskedRVV
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 05:41:08 PDT 2023
luke created this revision.
luke added reviewers: arcbbb, craig.topper, reames, frasercrmck.
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An IMPLICIT_DEF is different from an undef node, so this patch fixes the
check for it.
It doesn't actually change any test output, as previously it was
conservatively emitting tail undisturbed with an IMPLICIT_DEF passthru,
which ultimately got selected as tail agnostic anyway.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D152810
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3194,7 +3194,9 @@
if (!(N->getConstantOperandVal(*TailPolicyOpIdx) &
RISCVII::TAIL_AGNOSTIC)) {
// We can't use TA if the tie-operand is not IMPLICIT_DEF
- if (!N->getOperand(0).isUndef()) {
+ if (!(N->getOperand(0).isMachineOpcode() &&
+ N->getOperand(0).getMachineOpcode() ==
+ TargetOpcode::IMPLICIT_DEF)) {
// Keep the true-masked instruction when there is no unmasked TU
// instruction
if (I->UnmaskedTUPseudo == I->MaskedPseudo)
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