[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2
JinGu Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 02:08:48 PDT 2023
jaykang10 added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22446-22451
+ if (User->getOpcode() != ISD::EXTRACT_SUBVECTOR) {
+ HasFoundMULLow = false;
+ break;
+ }
+
+ if (!isNullConstant(User->getOperand(1))) {
----------------
dmgreen wrote:
> These two ifs could be combined into one
Let me update it.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22460
+ // Check ExtractLow's user.
+ if (HasFoundMULLow && ExtractLow->hasOneUse()) {
+ SDNode *ExtractLowUser = *ExtractLow.getNode()->use_begin();
----------------
dmgreen wrote:
> I think this one could leave HasFoundMULLow = true but without a valid TruncLow.
Let me update it.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150969/new/
https://reviews.llvm.org/D150969
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