[PATCH] D152688: [Aarch64] Add Cortex-A510 specific scheduling

[harvin iriawan via Phabricator via llvm-commits]

harviniriawan marked 2 inline comments as done.
harviniriawan added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:122
+// Load
+def : WriteRes<WriteLD, [CortexA510UnitLd]> { let Latency = 2; }
+def : WriteRes<WriteLDIdx, [CortexA510UnitLd]> { let Latency = 2; }
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dmgreen wrote:
> 2 sounds quite low. Is that better than using 3?
SWOG indicates that integer loads have latency of 2


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https://reviews.llvm.org/D152688