[PATCH] D152050: [RISCV] Begin removing hasDummyMask.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 12 12:02:15 PDT 2023
This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd170eff527d0: [RISCV] Begin removing hasDummyMask. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152050/new/
https://reviews.llvm.org/D152050
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3207,16 +3207,13 @@
unsigned Opc = UseTUPseudo ? I->UnmaskedTUPseudo : I->UnmaskedPseudo;
- // Check that we're dropping the mask operand and any policy operand
- // when we transform to this unmasked pseudo. Additionally, if this
- // instruction is tail agnostic, the unmasked instruction should not have a
- // tied destination.
+ // If this instruction is tail agnostic, the unmasked instruction should not
+ // have a tied destination.
#ifndef NDEBUG
const MCInstrDesc &MCID = TII.get(Opc);
uint64_t TSFlags = MCID.TSFlags;
bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
- assert(UseTUPseudo == HasTiedDest && RISCVII::hasDummyMaskOp(TSFlags) &&
- "Unexpected pseudo to transform to");
+ assert((UseTUPseudo == HasTiedDest) && "Unexpected pseudo to transform to");
#endif
SmallVector<SDValue, 8> Ops;
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -630,9 +630,8 @@
const MachineFunction *MF = MBB->getParent();
assert(MF && "MBB expected to be in a machine function");
- const TargetRegisterInfo *TRI =
- MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
-
+ const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+ const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
assert(TRI && "TargetRegisterInfo expected");
uint64_t TSFlags = MI->getDesc().TSFlags;
@@ -705,9 +704,16 @@
// Unmasked pseudo instructions need to append dummy mask operand to
// V instructions. All V instructions are modeled as the masked version.
- if (RISCVII::hasDummyMaskOp(TSFlags))
+ const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+ const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
+ if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
+ assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
+ RISCV::VMV0RegClassID &&
+ "Expected only mask operand to be missing");
OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
+ }
+ assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
return true;
}
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -140,10 +140,6 @@
static inline VLMUL getLMul(uint64_t TSFlags) {
return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
}
-/// \returns true if there is a dummy mask operand for the instruction.
-static inline bool hasDummyMaskOp(uint64_t TSFlags) {
- return TSFlags & HasDummyMaskOpMask;
-}
/// \returns true if tail agnostic is enforced for the instruction.
static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
return TSFlags & ForceTailAgnosticMask;
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