[llvm] 6b8850f - [RISCV] Remove HasDummyMask from tablegen files.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 12 12:02:04 PDT 2023
Author: Craig Topper
Date: 2023-06-12T11:57:44-07:00
New Revision: 6b8850f437d0e88767d3aaffd35a9b1ee3736e94
URL: https://github.com/llvm/llvm-project/commit/6b8850f437d0e88767d3aaffd35a9b1ee3736e94
DIFF: https://github.com/llvm/llvm-project/commit/6b8850f437d0e88767d3aaffd35a9b1ee3736e94.diff
LOG: [RISCV] Remove HasDummyMask from tablegen files.
This isn't needed after D152050.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D152218
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index b9f175c275286..0715dc4f9c194 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -64,12 +64,8 @@ enum {
VLMulShift = ConstraintShift + 3,
VLMulMask = 0b111 << VLMulShift,
- // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
- HasDummyMaskOpShift = VLMulShift + 3,
- HasDummyMaskOpMask = 1 << HasDummyMaskOpShift,
-
// Force a tail agnostic policy even this instruction has a tied destination.
- ForceTailAgnosticShift = HasDummyMaskOpShift + 1,
+ ForceTailAgnosticShift = VLMulShift + 3,
ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
// Does this instruction have a merge operand that must be removed when
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 6d9094e914b33..1e00808773063 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -187,36 +187,33 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
bits<3> VLMul = 0;
let TSFlags{10-8} = VLMul;
- bit HasDummyMask = 0;
- let TSFlags{11} = HasDummyMask;
-
bit ForceTailAgnostic = false;
- let TSFlags{12} = ForceTailAgnostic;
+ let TSFlags{11} = ForceTailAgnostic;
bit HasMergeOp = 0;
- let TSFlags{13} = HasMergeOp;
+ let TSFlags{12} = HasMergeOp;
bit HasSEWOp = 0;
- let TSFlags{14} = HasSEWOp;
+ let TSFlags{13} = HasSEWOp;
bit HasVLOp = 0;
- let TSFlags{15} = HasVLOp;
+ let TSFlags{14} = HasVLOp;
bit HasVecPolicyOp = 0;
- let TSFlags{16} = HasVecPolicyOp;
+ let TSFlags{15} = HasVecPolicyOp;
bit IsRVVWideningReduction = 0;
- let TSFlags{17} = IsRVVWideningReduction;
+ let TSFlags{16} = IsRVVWideningReduction;
bit UsesMaskPolicy = 0;
- let TSFlags{18} = UsesMaskPolicy;
+ let TSFlags{17} = UsesMaskPolicy;
// Indicates that the result can be considered sign extended from bit 31. Some
// instructions with this flag aren't W instructions, but are either sign
// extended from a smaller size, always outputs a small integer, or put zeros
// in bits 63:31. Used by the SExtWRemoval pass.
bit IsSignExtendingOpW = 0;
- let TSFlags{19} = IsSignExtendingOpW;
+ let TSFlags{18} = IsSignExtendingOpW;
}
// Pseudo instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index f8d17ace142e9..5028fa4b5ee2b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -685,7 +685,7 @@ class GetVTypePredicates<VTypeInfo vti> {
true : [HasVInstructions]);
}
-class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
+class VPseudoUSLoadNoMask<VReg RetClass, int EEW> :
Pseudo<(outs RetClass:$rd),
(ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
@@ -695,7 +695,6 @@ class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = DummyMask;
}
class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
@@ -708,7 +707,6 @@ class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -731,7 +729,7 @@ class VPseudoUSLoadMask<VReg RetClass, int EEW> :
let UsesMaskPolicy = 1;
}
-class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
+class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
@@ -741,7 +739,6 @@ class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = DummyMask;
}
class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
@@ -754,7 +751,6 @@ class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -787,7 +783,6 @@ class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
@@ -800,7 +795,6 @@ class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -835,7 +829,6 @@ class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
}
@@ -851,7 +844,6 @@ class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
}
@@ -875,7 +867,7 @@ class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let UsesMaskPolicy = 1;
}
-class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
+class VPseudoUSStoreNoMask<VReg StClass, int EEW>:
Pseudo<(outs),
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
@@ -885,7 +877,6 @@ class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = DummyMask;
}
class VPseudoUSStoreMask<VReg StClass, int EEW>:
@@ -910,7 +901,6 @@ class VPseudoSStoreNoMask<VReg StClass, int EEW>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoSStoreMask<VReg StClass, int EEW>:
@@ -925,33 +915,6 @@ class VPseudoSStoreMask<VReg StClass, int EEW>:
let HasSEWOp = 1;
}
-// Unary instruction that is never masked so HasDummyMask=0.
-class VPseudoUnaryNoDummyMask<VReg RetClass,
- DAGOperand Op2Class> :
- Pseudo<(outs RetClass:$rd),
- (ins Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
- RISCVVPseudo {
- let mayLoad = 0;
- let mayStore = 0;
- let hasSideEffects = 0;
- let HasVLOp = 1;
- let HasSEWOp = 1;
-}
-
-class VPseudoUnaryNoDummyMaskTU<VReg RetClass,
- DAGOperand Op2Class> :
- Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
- RISCVVPseudo {
- let mayLoad = 0;
- let mayStore = 0;
- let hasSideEffects = 0;
- let HasVLOp = 1;
- let HasSEWOp = 1;
- let HasMergeOp = 1;
- let Constraints = "$rd = $dest";
-}
-
class VPseudoNullaryNoMask<VReg RegClass>:
Pseudo<(outs RegClass:$rd),
(ins AVL:$vl, ixlenimm:$sew),
@@ -961,7 +924,6 @@ class VPseudoNullaryNoMask<VReg RegClass>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoNullaryNoMaskTU<VReg RegClass>:
@@ -974,7 +936,6 @@ class VPseudoNullaryNoMaskTU<VReg RegClass>:
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
}
@@ -1009,7 +970,8 @@ class VPseudoNullaryPseudoM<string BaseInst>
}
// RetClass could be GPR or VReg.
-class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
+class VPseudoUnaryNoMask<DAGOperand RetClass, DAGOperand OpClass,
+ string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
@@ -1019,11 +981,11 @@ class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint =
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
// RetClass could be GPR or VReg.
-class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
+class VPseudoUnaryNoMaskTU<DAGOperand RetClass, DAGOperand OpClass,
+ string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
@@ -1033,7 +995,6 @@ class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
}
@@ -1133,8 +1094,7 @@ class VPseudoUnaryAnyMask<VReg RetClass,
class VPseudoBinaryNoMask<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
- string Constraint,
- int DummyMask = 1> :
+ string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
@@ -1144,7 +1104,6 @@ class VPseudoBinaryNoMask<VReg RetClass,
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = DummyMask;
}
class VPseudoBinaryNoMaskTU<VReg RetClass,
@@ -1160,7 +1119,6 @@ class VPseudoBinaryNoMaskTU<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
}
@@ -1180,7 +1138,6 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
let Constraints = Join<[Constraint, "$rd = $rs2"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasVecPolicyOp = 1;
let isConvertibleToThreeAddress = 1;
}
@@ -1196,7 +1153,6 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1372,7 +1328,6 @@ class VPseudoTernaryNoMask<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
- let HasDummyMask = 1;
}
class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
@@ -1392,7 +1347,6 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
- let HasDummyMask = 1;
}
class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
@@ -1405,7 +1359,6 @@ class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1418,7 +1371,6 @@ class VPseudoUSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -1450,7 +1402,6 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1463,7 +1414,6 @@ class VPseudoUSSegLoadFFNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
@@ -1495,7 +1445,6 @@ class VPseudoSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
@@ -1508,7 +1457,6 @@ class VPseudoSSegLoadNoMaskTU<VReg RetClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $merge";
}
@@ -1545,7 +1493,6 @@ class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
let Constraints = "@earlyclobber $rd";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1562,7 +1509,6 @@ class VPseudoISegLoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMU
let Constraints = "@earlyclobber $rd, $rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
let HasMergeOp = 1;
}
@@ -1597,7 +1543,6 @@ class VPseudoUSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoUSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1623,7 +1568,6 @@ class VPseudoSSegStoreNoMask<VReg ValClass, int EEW, bits<4> NF>:
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoSSegStoreMask<VReg ValClass, int EEW, bits<4> NF>:
@@ -1651,7 +1595,6 @@ class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
- let HasDummyMask = 1;
}
class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1715,7 +1658,7 @@ multiclass VPseudoLoadMask {
defvar mx = mti.LMul.MX;
defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
let VLMul = mti.LMul.value in {
- def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
+ def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1>,
Sched<[WriteVLDM_MX, ReadVLDX]>;
}
}
@@ -1794,7 +1737,7 @@ multiclass VPseudoStoreMask {
defvar mx = mti.LMul.MX;
defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
let VLMul = mti.LMul.value in {
- def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
+ def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, /*EEW*/1>,
Sched<[WriteVSTM_MX, ReadVSTX]>;
}
}
@@ -2098,7 +2041,7 @@ multiclass VPseudoVALU_MM {
defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
let VLMul = m.value in {
- def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "", /*DummyMask*/0>,
+ def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
}
}
@@ -2252,17 +2195,17 @@ multiclass VPseudoUnaryVMV_V_X_I {
defvar ReadVIMovX_MX = !cast<SchedRead>("ReadVIMovX_" # mx);
let VLMul = m.value in {
- def "_V_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, m.vrclass>,
+ def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
- def "_X_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, GPR>,
+ def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>,
Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
- def "_I_" # mx : VPseudoUnaryNoDummyMask<m.vrclass, simm5>,
+ def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,
Sched<[WriteVIMovI_MX]>;
- def "_V_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, m.vrclass>,
+ def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVIMovV_MX, ReadVIMovV_MX]>;
- def "_X_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, GPR>,
+ def "_X_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, GPR>,
Sched<[WriteVIMovX_MX, ReadVIMovX_MX]>;
- def "_I_" # mx # "_TU": VPseudoUnaryNoDummyMaskTU<m.vrclass, simm5>,
+ def "_I_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, simm5>,
Sched<[WriteVIMovI_MX]>;
}
}
@@ -2278,10 +2221,10 @@ multiclass VPseudoVMV_F {
let VLMul = m.value in {
def "_" # f.FX # "_" # mx :
- VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>,
+ VPseudoUnaryNoMask<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>;
def "_" # f.FX # "_" # mx # "_TU":
- VPseudoUnaryNoDummyMaskTU<m.vrclass, f.fprclass>,
+ VPseudoUnaryNoMaskTU<m.vrclass, f.fprclass>,
Sched<[WriteVFMovV_MX, ReadVFMovF_MX]>;
}
}
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