[llvm] c5fdab3 - [RISCV] Use tail undisturbed vmv.v.v instead of vadd.vi with 0 for vp.merge with all ones mask.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 12 10:27:27 PDT 2023
Author: Craig Topper
Date: 2023-06-12T10:27:08-07:00
New Revision: c5fdab30143aeb45fc4bfebc9fcd551127e0c569
URL: https://github.com/llvm/llvm-project/commit/c5fdab30143aeb45fc4bfebc9fcd551127e0c569
DIFF: https://github.com/llvm/llvm-project/commit/c5fdab30143aeb45fc4bfebc9fcd551127e0c569.diff
LOG: [RISCV] Use tail undisturbed vmv.v.v instead of vadd.vi with 0 for vp.merge with all ones mask.
No idea what I was thinking when I suggested vadd.vi.
Reviewed By: reames, frasercrmck, fakepaper56
Differential Revision: https://reviews.llvm.org/D152553
Added:
llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
Removed:
llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vadd.ll
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 27269be559822..a27cb80a9f9d8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3408,44 +3408,31 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
}
// Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to
-// (VADD_VI_<LMUL>_TU false, true, 0, vl, sew). It may decrease uses of VMSET.
-bool RISCVDAGToDAGISel::performVMergeToVAdd(SDNode *N) {
+// (MMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
+bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) {
+#define CASE_VMERGE_TO_VMV(lmul) \
+ case RISCV::PseudoVMERGE_VVM_##lmul##_TU: \
+ NewOpc = RISCV::PseudoVMV_V_V_##lmul##_TU; \
+ break;
unsigned NewOpc;
switch (N->getMachineOpcode()) {
default:
llvm_unreachable("Expected VMERGE_VVM_<LMUL>_TU instruction.");
- case RISCV::PseudoVMERGE_VVM_MF8_TU:
- NewOpc = RISCV::PseudoVADD_VI_MF8_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_MF4_TU:
- NewOpc = RISCV::PseudoVADD_VI_MF4_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_MF2_TU:
- NewOpc = RISCV::PseudoVADD_VI_MF2_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_M1_TU:
- NewOpc = RISCV::PseudoVADD_VI_M1_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_M2_TU:
- NewOpc = RISCV::PseudoVADD_VI_M2_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_M4_TU:
- NewOpc = RISCV::PseudoVADD_VI_M4_TU;
- break;
- case RISCV::PseudoVMERGE_VVM_M8_TU:
- NewOpc = RISCV::PseudoVADD_VI_M8_TU;
- break;
+ CASE_VMERGE_TO_VMV(MF8)
+ CASE_VMERGE_TO_VMV(MF4)
+ CASE_VMERGE_TO_VMV(MF2)
+ CASE_VMERGE_TO_VMV(M1)
+ CASE_VMERGE_TO_VMV(M2)
+ CASE_VMERGE_TO_VMV(M4)
+ CASE_VMERGE_TO_VMV(M8)
}
if (!usesAllOnesMask(N, /* MaskOpIdx */ 3))
return false;
- SDLoc DL(N);
- EVT VT = N->getValueType(0);
- SDValue Ops[] = {N->getOperand(1), N->getOperand(2),
- CurDAG->getTargetConstant(0, DL, Subtarget->getXLenVT()),
- N->getOperand(4), N->getOperand(5)};
- SDNode *Result = CurDAG->getMachineNode(NewOpc, DL, VT, Ops);
+ SDNode *Result = CurDAG->getMachineNode(
+ NewOpc, SDLoc(N), N->getValueType(0),
+ {N->getOperand(1), N->getOperand(2), N->getOperand(4), N->getOperand(5)});
ReplaceUses(N, Result);
return true;
}
@@ -3486,7 +3473,7 @@ bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() {
IsVMergeTA(Opc))
MadeChange |= performCombineVMergeAndVOps(N, IsVMergeTA(Opc));
if (IsVMergeTU(Opc) && N->getOperand(0) == N->getOperand(1))
- MadeChange |= performVMergeToVAdd(N);
+ MadeChange |= performVMergeToVMv(N);
}
return MadeChange;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index ad93ae8749584..38324b82d3444 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -181,7 +181,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool doPeepholeSExtW(SDNode *Node);
bool doPeepholeMaskedRVV(SDNode *Node);
bool doPeepholeMergeVVMFold();
- bool performVMergeToVAdd(SDNode *N);
+ bool performVMergeToVMv(SDNode *N);
bool performCombineVMergeAndVOps(SDNode *N, bool IsTA);
};
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vadd.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
similarity index 95%
rename from llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vadd.ll
rename to llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
index 74af996a222df..f2adf27dad6ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
@@ -4,7 +4,7 @@ define <vscale x 1 x i8> @vpmerge_mf8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y
; CHECK-LABEL: vpmerge_mf8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
-; CHECK-NEXT: vadd.vi v8, v9, 0
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%splat = insertelement <vscale x 1 x i1> poison, i1 -1, i8 0
%allones = shufflevector <vscale x 1 x i1> %splat, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
@@ -16,7 +16,7 @@ define <vscale x 2 x i8> @vpmerge_mf4(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y
; CHECK-LABEL: vpmerge_mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
-; CHECK-NEXT: vadd.vi v8, v9, 0
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i8 0
%allones = shufflevector <vscale x 2 x i1> %splat, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
@@ -28,7 +28,7 @@ define <vscale x 4 x i8> @vpmerge_mf2(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y
; CHECK-LABEL: vpmerge_mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
-; CHECK-NEXT: vadd.vi v8, v9, 0
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%splat = insertelement <vscale x 4 x i1> poison, i1 -1, i8 0
%allones = shufflevector <vscale x 4 x i1> %splat, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
@@ -40,7 +40,7 @@ define <vscale x 8 x i8> @vpmerge_m1(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y,
; CHECK-LABEL: vpmerge_m1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT: vadd.vi v8, v9, 0
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%splat = insertelement <vscale x 8 x i1> poison, i1 -1, i8 0
%allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
@@ -52,7 +52,7 @@ define <vscale x 8 x i16> @vpmerge_m2(<vscale x 8 x i16> %x, <vscale x 8 x i16>
; CHECK-LABEL: vpmerge_m2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; CHECK-NEXT: vadd.vi v8, v10, 0
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%splat = insertelement <vscale x 8 x i1> poison, i1 -1, i16 0
%allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
@@ -64,7 +64,7 @@ define <vscale x 8 x i32> @vpmerge_m4(<vscale x 8 x i32> %x, <vscale x 8 x i32>
; CHECK-LABEL: vpmerge_m4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
-; CHECK-NEXT: vadd.vi v8, v12, 0
+; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
%splat = insertelement <vscale x 8 x i1> poison, i1 -1, i32 0
%allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
@@ -76,7 +76,7 @@ define <vscale x 8 x i64> @vpmerge_m8(<vscale x 8 x i64> %x, <vscale x 8 x i64>
; CHECK-LABEL: vpmerge_m8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
-; CHECK-NEXT: vadd.vi v8, v16, 0
+; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%splat = insertelement <vscale x 8 x i1> poison, i1 -1, i64 0
%allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
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