[llvm] b2195bc - [SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM

[Anna Thomas via llvm-commits]

Author: Anna Thomas
Date: 2023-06-12T12:22:21-04:00
New Revision: b2195bc771ede9d0229b0796fe41d3a7da18d3ec

URL: https://github.com/llvm/llvm-project/commit/b2195bc771ede9d0229b0796fe41d3a7da18d3ec
DIFF: https://github.com/llvm/llvm-project/commit/b2195bc771ede9d0229b0796fe41d3a7da18d3ec.diff

LOG: [SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM

The missing legalization in SelectionDAG was identified when adding the
intrinsic support for vector reduction for maximum/minimum (D152370).

Fixes part of PR: https://github.com/llvm/llvm-project/issues/63267

Differential Revision: https://reviews.llvm.org/D152718

Added: 
    llvm/test/CodeGen/AArch64/fmaximum-legalization.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index d902b358526bd..b21a89bedc6e2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4167,6 +4167,9 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
                     RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                     RTLIB::FMIN_PPCF128, Results);
     break;
+  // FIXME: We do not have libcalls for FMAXIMUM and FMINIMUM. So, we cannot use
+  // libcall legalization for these nodes, but there is no default expasion for
+  // these nodes either (see PR63267 for example).
   case ISD::FMAXNUM:
   case ISD::STRICT_FMAXNUM:
     ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
@@ -4951,6 +4954,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
   case ISD::FREM:
   case ISD::FMINNUM:
   case ISD::FMAXNUM:
+  case ISD::FMINIMUM:
+  case ISD::FMAXIMUM:
   case ISD::FPOW:
     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
     Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));

diff  --git a/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll b/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
new file mode 100644
index 0000000000000..fa86e6ceec1af
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+
+declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)
+
+declare <2 x fp128> @llvm.maximum.v2f128(<2 x fp128>, <2 x fp128>)
+
+; Fixes PR63267
+define <4 x half> @fmaximum_v4f16(<4 x half> %x, <4 x half> %y) {
+; CHECK-LABEL: fmaximum_v4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    mov h2, v1.h[1]
+; CHECK-NEXT:    mov h3, v0.h[1]
+; CHECK-NEXT:    fcvt s4, h1
+; CHECK-NEXT:    fcvt s5, h0
+; CHECK-NEXT:    mov h6, v1.h[2]
+; CHECK-NEXT:    mov h7, v0.h[2]
+; CHECK-NEXT:    mov h1, v1.h[3]
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    fmax s4, s5, s4
+; CHECK-NEXT:    fcvt s5, h7
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fmax s2, s3, s2
+; CHECK-NEXT:    fcvt s3, h6
+; CHECK-NEXT:    mov h6, v0.h[3]
+; CHECK-NEXT:    fcvt h0, s4
+; CHECK-NEXT:    fcvt h2, s2
+; CHECK-NEXT:    fmax s3, s5, s3
+; CHECK-NEXT:    fcvt s4, h6
+; CHECK-NEXT:    mov v0.h[1], v2.h[0]
+; CHECK-NEXT:    fcvt h2, s3
+; CHECK-NEXT:    fmax s1, s4, s1
+; CHECK-NEXT:    mov v0.h[2], v2.h[0]
+; CHECK-NEXT:    fcvt h1, s1
+; CHECK-NEXT:    mov v0.h[3], v1.h[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %r = call <4 x half> @llvm.maximum.v4f16(<4 x half> %x, <4 x half> %y)
+  ret <4 x half> %r
+}