[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22381
+// Try to combine op with uzp1.
+static SDValue tryCombineOpWithUZP1(SDNode *N,
+                                    TargetLowering::DAGCombinerInfo &DCI,
----------------
Perhaps name this tryCombineMULLWithUZP1, to show it operands on mull nodes.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22437
+  SDValue EXTRACTHIGHSrcVec = EXTRACTHIGH.getOperand(0);
+  if (EXTRACTHIGHSrcVec->use_size() != 2)
+    return SDValue();
----------------
If these or the conditions below fail, could it still create the UZP with an undef operand?
Something like this in pseudocode.
```
SDValue TRUNCLOWOP = DAG.getUndef(VT);
if (.. find the other operand through the uses) // This is the complex bit
  TRUNCLOWOP = Found Other Op;
UZP = DAG.getNode(AArch64ISD::UZP1, DL, UZP1VT, TRUNCLOWOP, TRUNCHIGHOP);
ReplaceUse(TRUNCHIGH, UZP EXTRACT_SUBVECTOR Hi).
if (previouslyFoundOtherOp)
  ReplaceUse(TRUNCLOW, UZP EXTRACT_SUBVECTOR Lo).
```
I believe that should then handle some of the other cases like efriedma mentioned.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22451
+
+    if (ConstantSDNode *IdxCst =
+            dyn_cast<ConstantSDNode>(User->getOperand(1))) {
----------------
This could use isNullConstant


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22492
+  // Create uzp1, extract_high and extract_low.
+  EVT TRUNCHIGHVT = TRUNCHIGH.getValueType();
+  EVT TRUNCLOWVT = TRUNCLOW.getValueType();
----------------
The LLVM naming scheme would be TruncHighVT I think.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150969/new/

https://reviews.llvm.org/D150969