[llvm] 2802739 - [NFC] Replace ;; with ;
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 11 02:25:30 PDT 2023
Author: David Green
Date: 2023-06-11T10:25:24+01:00
New Revision: 2802739dfd844ee6a5148c25c74a58e3f9f27448
URL: https://github.com/llvm/llvm-project/commit/2802739dfd844ee6a5148c25c74a58e3f9f27448
DIFF: https://github.com/llvm/llvm-project/commit/2802739dfd844ee6a5148c25c74a58e3f9f27448.diff
LOG: [NFC] Replace ;; with ;
Added:
Modified:
llvm/lib/Analysis/Loads.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/lib/Transforms/Scalar/GVN.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Analysis/Loads.cpp b/llvm/lib/Analysis/Loads.cpp
index 0dd08dee47447..ab49891c7f85c 100644
--- a/llvm/lib/Analysis/Loads.cpp
+++ b/llvm/lib/Analysis/Loads.cpp
@@ -680,7 +680,7 @@ Value *llvm::FindAvailableLoadedValue(LoadInst *Load, AAResults &AA,
// Try to find an available value first, and delay expensive alias analysis
// queries until later.
- Value *Available = nullptr;;
+ Value *Available = nullptr;
SmallVector<Instruction *> MustNotAliasInsts;
for (Instruction &Inst : make_range(++Load->getReverseIterator(),
ScanBB->rend())) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index 0252fbb84e296..ce6d9549cf51a 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -1399,8 +1399,8 @@ void DwarfCompileUnit::createAbstractEntity(const DINode *Node,
assert(Scope && Scope->isAbstractScope());
auto &Entity = getAbstractEntities()[Node];
if (isa<const DILocalVariable>(Node)) {
- Entity = std::make_unique<DbgVariable>(
- cast<const DILocalVariable>(Node), nullptr /* IA */);;
+ Entity = std::make_unique<DbgVariable>(cast<const DILocalVariable>(Node),
+ nullptr /* IA */);
DU->addScopeVariable(Scope, cast<DbgVariable>(Entity.get()));
} else if (isa<const DILabel>(Node)) {
Entity = std::make_unique<DbgLabel>(
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c38951a168db9..cb555d87345e7 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -7520,7 +7520,7 @@ LegalizerHelper::lowerVectorReduction(MachineInstr &MI) {
Observer.changedInstr(MI);
return Legalized;
}
- return UnableToLegalize;;
+ return UnableToLegalize;
}
static bool shouldLowerMemFuncForSize(const MachineFunction &MF) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
index 5984a99e8aee8..a640e6938fb05 100644
--- a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
@@ -489,7 +489,7 @@ lowerIncomingStatepointValue(SDValue Incoming, bool RequireSpillSlot,
Ops.push_back(std::get<0>(Res));
if (auto *MMO = std::get<2>(Res))
MemRefs.push_back(MMO);
- Chain = std::get<1>(Res);;
+ Chain = std::get<1>(Res);
Builder.DAG.setRoot(Chain);
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 1b54e2cb2b292..86279ba018048 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4128,13 +4128,13 @@ AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
if (!MCE) {
TokError("immediate value expected for vector index");
- return MatchOperand_ParseFail;;
+ return MatchOperand_ParseFail;
}
SMLoc E = getLoc();
if (parseToken(AsmToken::RBrac, "']' expected"))
- return MatchOperand_ParseFail;;
+ return MatchOperand_ParseFail;
Operands.push_back(AArch64Operand::CreateVectorIndex(MCE->getValue(), SIdx,
E, getContext()));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 86abd0f319b4c..25e188fb02ca2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2755,7 +2755,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
uint64_t Lit = cast<ConstantFPSDNode>(Lo)->getValueAPF()
.bitcastToAPInt().getZExtValue();
if (AMDGPU::isInlinableLiteral32(Lit, Subtarget->hasInv2PiInlineImm())) {
- Src = CurDAG->getTargetConstant(Lit, SDLoc(In), MVT::i64);;
+ Src = CurDAG->getTargetConstant(Lit, SDLoc(In), MVT::i64);
SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 1b6d050efe183..97b3161c7f98b 100644
--- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -759,7 +759,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
break;
SdwaSel DstSel = static_cast<SdwaSel>(
- TII->getNamedImmOperand(*SDWAInst, AMDGPU::OpName::dst_sel));;
+ TII->getNamedImmOperand(*SDWAInst, AMDGPU::OpName::dst_sel));
SdwaSel OtherDstSel = static_cast<SdwaSel>(
TII->getNamedImmOperand(*OtherInst, AMDGPU::OpName::dst_sel));
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index d628936cee01b..fa626a775c838 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -171,7 +171,7 @@ bool BPFDAGToDAGISel::SelectInlineAsmMemoryOperand(
}
SDLoc DL(Op);
- SDValue AluOp = CurDAG->getTargetConstant(ISD::ADD, DL, MVT::i32);;
+ SDValue AluOp = CurDAG->getTargetConstant(ISD::ADD, DL, MVT::i32);
OutOps.push_back(Op0);
OutOps.push_back(Op1);
OutOps.push_back(AluOp);
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 3753bee76777e..6599970361700 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -3626,7 +3626,7 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
break;
case HexagonISD::VINSERTW0:
if (isUndef(Ops[1]))
- return Ops[0];;
+ return Ops[0];
break;
case HexagonISD::VROR: {
if (Ops[0].getOpcode() == HexagonISD::VROR) {
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 7ab8b3c4d0e95..58dbb0092857a 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -269,7 +269,7 @@ DemandedFields getDemanded(const MachineInstr &MI,
DemandedFields Res;
// Start conservative if registers are used
if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VL))
- Res.demandVL();;
+ Res.demandVL();
if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VTYPE))
Res.demandVTYPE();
// Start conservative on the unlowered form too
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 8380f0001273e..289642ac37bbf 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -144,7 +144,7 @@ class X86AsmBackend : public MCAsmBackend {
// jumps, and (unfused) conditional jumps with nops. Both the
// instructions aligned and the alignment method (nop vs prefix) may
// change in the future.
- AlignBoundary = assumeAligned(32);;
+ AlignBoundary = assumeAligned(32);
AlignBranchType.addKind(X86::AlignBranchFused);
AlignBranchType.addKind(X86::AlignBranchJcc);
AlignBranchType.addKind(X86::AlignBranchJmp);
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index f811ee58159fa..9f9dc539533ff 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -9199,7 +9199,7 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
DIExpression::appendOffset(Ops, Offset);
Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
- return ParamLoadedValue(*Op, Expr);;
+ return ParamLoadedValue(*Op, Expr);
}
case X86::MOV8ri:
case X86::MOV16ri:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 32fb80c98dc69..7719158f693a6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1775,7 +1775,7 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
// If we've proven all of the lanes undef, return an undef value.
// TODO: Intersect w/demanded lanes
if (UndefElts.isAllOnes())
- return UndefValue::get(I->getType());;
+ return UndefValue::get(I->getType());
return MadeChange ? I : nullptr;
}
diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp
index 54be8e3be87e9..318788db40c5e 100644
--- a/llvm/lib/Transforms/Scalar/GVN.cpp
+++ b/llvm/lib/Transforms/Scalar/GVN.cpp
@@ -1954,7 +1954,7 @@ static bool impliesEquivalanceIfTrue(CmpInst* Cmp) {
if (isa<ConstantFP>(LHS) && !cast<ConstantFP>(LHS)->isZero())
return true;
if (isa<ConstantFP>(RHS) && !cast<ConstantFP>(RHS)->isZero())
- return true;;
+ return true;
// TODO: Handle vector floating point constants
}
return false;
@@ -1980,7 +1980,7 @@ static bool impliesEquivalanceIfFalse(CmpInst* Cmp) {
if (isa<ConstantFP>(LHS) && !cast<ConstantFP>(LHS)->isZero())
return true;
if (isa<ConstantFP>(RHS) && !cast<ConstantFP>(RHS)->isZero())
- return true;;
+ return true;
// TODO: Handle vector floating point constants
}
return false;
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