[llvm] edd08f1 - [RISCV][NFC] Fix typo in RISCVAsmPrinter::emitNTLHint
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 11 01:46:29 PDT 2023
Author: Yingwei Zheng
Date: 2023-06-11T16:43:15+08:00
New Revision: edd08f17c36ecaefc7d48c0eb80fb92550b62c76
URL: https://github.com/llvm/llvm-project/commit/edd08f17c36ecaefc7d48c0eb80fb92550b62c76
DIFF: https://github.com/llvm/llvm-project/commit/edd08f17c36ecaefc7d48c0eb80fb92550b62c76.diff
LOG: [RISCV][NFC] Fix typo in RISCVAsmPrinter::emitNTLHint
Added:
Modified:
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 30aed87bb67db..d777bfba655b8 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -102,7 +102,7 @@ void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
// instructions) auto-generated.
#include "RISCVGenMCPseudoLowering.inc"
-// If the target supports Zihintnthl and the instruction has a nontemporal
+// If the target supports Zihintntl and the instruction has a nontemporal
// MachineMemOperand, emit an NTLH hint instruction before it.
void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
if (!STI->hasStdExtZihintntl())
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