[PATCH] D147678: [LegalizeTypes][AArch64] Use scalar_to_vector to eliminate bitcast

[Allen zhong via Phabricator via llvm-commits]

Allen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22895
+    Results.push_back(DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Op));
+    return;
+  }
----------------
efriedma wrote:
> SCALAR_TO_VECTOR from i32 to v2i16 implicitly discards the high 16 bits of the input.  (The other lane is UNDEF.  UNDEF might happen to be what you want in simple cases, but it won't be in general.)
> 
> Something like `(v2i16 extract_subvector (v4i16 bitcast (v2i32 scalar_to_vector (i32 in))), 0)` should have the semantics you want, and lower to something reasonably efficient.
Thanks, apply your comment.
The extra instruction **ushll v0.4s, v0.4h, #0** for **(v4i32 any_extend v4i16)** will clear the other lane.
```
            t2: i32,ch = CopyFromReg t0, Register:i32 %0
          t8: v2i32 = scalar_to_vector t2
        t9: v4i16 = bitcast t8
      t20: v4i32 = any_extend t9
    t21: v2i32 = extract_subvector t20, Constant:i64<0>
```


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  https://reviews.llvm.org/D147678/new/

https://reviews.llvm.org/D147678