[PATCH] D147678: [LegalizeTypes][AArch64] Use scalar_to_vector to eliminate bitcast

[Allen zhong via Phabricator via llvm-commits]

Allen updated this revision to Diff 530172.
Allen added a comment.

(v2i16 extract_subvector (v4i16 bitcast (v2i32 scalar_to_vector (i32 in))), 0)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147678/new/

https://reviews.llvm.org/D147678

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/neon-bitcast.ll


Index: llvm/test/CodeGen/AArch64/neon-bitcast.ll
===================================================================
--- llvm/test/CodeGen/AArch64/neon-bitcast.ll
+++ llvm/test/CodeGen/AArch64/neon-bitcast.ll
@@ -572,3 +572,13 @@
   ret <16 x i8> %val
 }
 
+define <2 x i16> @bitcast_from_int(i32 %word) {
+; CHECK-LABEL: bitcast_from_int:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov s0, w0
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %ret = bitcast i32 %word to <2 x i16>
+  ret <2 x i16> %ret
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1228,6 +1228,8 @@
     setOperationAction(ISD::BITCAST, MVT::i8, Custom);
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
+    setOperationAction(ISD::BITCAST, MVT::v2i16, Custom);
+
     setLoadExtAction(ISD::EXTLOAD,  MVT::v4i16, MVT::v4i8, Custom);
     setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
     setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
@@ -22887,6 +22889,16 @@
   EVT VT = N->getValueType(0);
   EVT SrcVT = Op.getValueType();
 
+  if (VT == MVT::v2i16 && SrcVT == MVT::i32) {
+    // Use SCALAR_TO_VECTOR for lane zero
+    SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2i32, Op);
+    SDValue CastVal = DAG.getNode(ISD::BITCAST, DL, MVT::v4i16, Vec);
+    SDValue IdxZero = DAG.getConstant(0, DL, MVT::i64);
+    Results.push_back(
+        DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, CastVal, IdxZero));
+    return;
+  }
+
   if (VT.isScalableVector() && !isTypeLegal(VT) && isTypeLegal(SrcVT)) {
     assert(!VT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
            "Expected fp->int bitcast!");


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