[PATCH] D152565: [RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: luke, reames, frasercrmck.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

vslideup has a vector overlap constraint that vmv.v.v doesn't.
vmv.v.v is also a simpler instruction so may have better
throughput and/or latency in some CPUs.

This is an alternative to D152298 <https://reviews.llvm.org/D152298>, D152368 <https://reviews.llvm.org/D152368>, and D152496 <https://reviews.llvm.org/D152496>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152565

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

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