[PATCH] D151449: [RISCV] Add DAG combine for CTTZ in the case of input 0

[Mikhail Gudim via Phabricator via llvm-commits]

mgudim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11430
+
+  if (Op3.getOpcode() == ISD::TRUNCATE || Op3.getOpcode() == ISD::ZERO_EXTEND) {
+    CTTZ = Op3.getOperand(0);
----------------
craig.topper wrote:
> ```
> SDValue CTTZ = N->getOperand(2);
> if (CTTZ.getOpcode() == ISD::TRUNCATE || CTTZ.getOpcode() == ISD::ZERO_EXTEND)
>   CTTZ = CTTZ.getOperand(0);
> ```
can you please give the example IR when we see `ZERO_EXTEND` or `TRUNCATE`?


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  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449