[PATCH] D150324: [X86] Make constant `mul` -> `shl` + `add`/`sub` work for vector types

[Phoebe Wang via Phabricator via llvm-commits]

pengfei accepted this revision.
pengfei added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48707-48710
+    if (VT.isVector() && VT.isSimple()) {
+      EVT EleVT = VT.getVectorElementType();
+      if (EleVT != MVT::i8 && EleVT != MVT::i16 && EleVT != MVT::i32 &&
+          EleVT != MVT::i64)
----------------
Maybe just `VT.isVector() && VT.isInteger()` given we made sure it's legal type by line 48691.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48722-48724
+      if (auto *RawC = getTargetConstantFromNode(N->getOperand(1)))
+        if (auto *SplatC = RawC->getSplatValue())
+          C = &(SplatC->getUniqueInteger());
----------------
In which case we need to analyze target constant?


Repository:
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  https://reviews.llvm.org/D150324/new/

https://reviews.llvm.org/D150324