[PATCH] D152411: [RISCV] Fix crash in lowerVECTOR_INTERLEAVE when VecVT is an LMUL=8 type.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7697
 
+  // If the VT is LMUL=8, we need to split and reassemble.
+  if (VecVT.getSizeInBits().getKnownMinValue() == (8 * RISCV::RVVBitsPerBlock)) {
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fakepaper56 wrote:
> Whist is the reason that we don't expand LMUL=8 VECTOR_INTERLEAVE? I think `DAGTypeLegalizer::SplitVecRes_VECTOR_DEINTERLEAVE` does the same job.
The ISD::VECTOR_INTERLEAVE node takes 2 inputs and produces 2 results with the same number of elements. This is different than IR where it's 2 inputs and 1 result with 2 twice as many elements.

The test cases that crash started in IR as interleaving 2 MUL=8 types to produce a LMUL=16 result. In SelectionDAG this is represented as 2 LMUL=8 inputs and 2 LMUL=8 outputs. Type legalization only sees the LMUL=8 types so all the types looks legal.

The RISC-V lowering code concatenates the 2 LMUL=8 values into an LMUL=16 type which crashes because that isn't a legal type.

This patch splits the inputs into LMUL=4 pieces and creates to INTERLEAVE operations. When each of the INTERLEAVE operations is then lowered the concatenation will only produce an LMUL=8 type.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152411/new/

https://reviews.llvm.org/D152411