[PATCH] D152411: [RISCV] Fix crash in lowerVECTOR_INTERLEAVE when VecVT is an LMUL=8 type.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7697
 
+  // If the VT is LMUL=8, we need to split and reassemble.
+  if (VecVT.getSizeInBits().getKnownMinValue() == (8 * RISCV::RVVBitsPerBlock)) {
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Whist is the reason that we don't expand LMUL=8 VECTOR_INTERLEAVE? I think `DAGTypeLegalizer::SplitVecRes_VECTOR_DEINTERLEAVE` does the same job.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D152411/new/

https://reviews.llvm.org/D152411