[PATCH] D152370: [Intrinsic] Introduce reduction intrinsics for minimum/maximum

[Anna Thomas via Phabricator via llvm-commits]

anna added a comment.

> You do need to add VECREDUCE nodes for this. The ExpandReductions pass is considered legacy functionality, mostly for use by X86. Targets like AArch64 do not use it and rely on VECREDUCE legalization instead.

I'm not really sure we need to introduce a node for this, since we have  a generic lowering using the series of shuffles and vectorized fminimum.
There is a TTI hook for expanding reductions based on the intrinsic `TTI->shouldExpandReduction(II)`, which calls to various <Target>TTIImpl (it's false for most targets except RISCV and X86). 
We can change `shouldExpandReduction` for all targets <Target>TTIImpl that do support fminimum/fmaximum and the base TTIImpl as well (for new targets).

I'm just curious what does relying on legalization helps with? Is it just a cleaner approach?


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  https://reviews.llvm.org/D152370/new/

https://reviews.llvm.org/D152370