[PATCH] D151782: Improve WebAssembly vector bitmask, mask reduction, and extending
Caleb Zulawski via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 7 09:26:10 PDT 2023
calebzulawski added a comment.
Thanks! By the way, I don't have commit access to the repo, if you are able to commit for me.
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Comment at: llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll:27-30
+; CHECK-NEXT: i32.const $push0=, 15
+; CHECK-NEXT: i16x8.shl $push1=, $0, $pop0
+; CHECK-NEXT: i32.const $push4=, 15
+; CHECK-NEXT: i16x8.shr_s $push2=, $pop1, $pop4
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tlively wrote:
> Could we skip this sign extension before the `v128.any_true`? As long as the high bits of each input lane are zeroed (which I believe they should be), the sign extension doesn't affect the outcome of `v128.any_true`.
I originally thought this as well, but I think the shifts are inserted because the other lanes are undef instead of zero, if that's possible. I added the case at the end (test_cmp_v16i8) where all bits are known, and the shifts disappear.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D151782/new/
https://reviews.llvm.org/D151782
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