[PATCH] D151782: Improve WebAssembly vector bitmask, mask reduction, and extending

[Thomas Lively via Phabricator via llvm-commits]

tlively accepted this revision.
tlively added a comment.
This revision is now accepted and ready to land.

This looks really good! It's nice to see the improved codegen on the existing tests.



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Comment at: llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll:27-30
+; CHECK-NEXT:    i32.const $push0=, 15
+; CHECK-NEXT:    i16x8.shl $push1=, $0, $pop0
+; CHECK-NEXT:    i32.const $push4=, 15
+; CHECK-NEXT:    i16x8.shr_s $push2=, $pop1, $pop4
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Could we skip this sign extension before the `v128.any_true`? As long as the high bits of each input lane are zeroed (which I believe they should be), the sign extension doesn't affect the outcome of `v128.any_true`.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D151782