[llvm] bb10612 - [RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-06T13:30:33-07:00
New Revision: bb10612587f2b6c1cde3bce810ed7fb3f533f33b

URL: https://github.com/llvm/llvm-project/commit/bb10612587f2b6c1cde3bce810ed7fb3f533f33b
DIFF: https://github.com/llvm/llvm-project/commit/bb10612587f2b6c1cde3bce810ed7fb3f533f33b.diff

LOG: [RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.

This requires Zbkb.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152293

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    llvm/test/CodeGen/RISCV/rv64zbkb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index d237d47e0513e..e0d38993021a7 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -249,6 +249,21 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
     }
   }
 
+  // If the Low and High halves are the same, use pack. The pack instruction
+  // packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the
+  // lower half and rs2 in the upper half.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbkb]) {
+    int64_t LoVal = SignExtend64<32>(Val);
+    int64_t HiVal = SignExtend64<32>(Val >> 32);
+    if (LoVal == HiVal) {
+      RISCVMatInt::InstSeq TmpSeq;
+      generateInstSeqImpl(LoVal, ActiveFeatures, TmpSeq);
+      TmpSeq.emplace_back(RISCV::PACK, 0);
+      if (TmpSeq.size() < Res.size())
+        Res = TmpSeq;
+    }
+  }
+
   // Perform optimization with BCLRI/BSETI in the Zbs extension.
   if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
     // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
@@ -402,6 +417,7 @@ OpndKind Inst::getOpndKind() const {
   case RISCV::SH1ADD:
   case RISCV::SH2ADD:
   case RISCV::SH3ADD:
+  case RISCV::PACK:
     return RISCVMatInt::RegReg;
   case RISCV::ADDI:
   case RISCV::ADDIW:

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
index 766a7dfafe615..fa96c576017ba 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -290,3 +290,21 @@ define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroe
   %8 = or i32 %6, %7
   ret i32 %8
 }
+
+define i64 @pack_i64_imm() {
+; RV64I-LABEL: pack_i64_imm:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, 65793
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    slli a1, a0, 32
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pack_i64_imm:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    lui a0, 65793
+; RV64ZBKB-NEXT:    addiw a0, a0, 16
+; RV64ZBKB-NEXT:    pack a0, a0, a0
+; RV64ZBKB-NEXT:    ret
+  ret i64 1157442765409226768 ; 0x0101010101010101
+}