[llvm] 4f5f38b - [RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-06T13:23:17-07:00
New Revision: 4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96

URL: https://github.com/llvm/llvm-project/commit/4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96
DIFF: https://github.com/llvm/llvm-project/commit/4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96.diff

LOG: [RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions.

This avoids checking the size of the sequence repeatedly for each
special case. Especially on RV32 where none of the special cases
apply.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152300

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 95c8098829a65..d237d47e0513e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -197,11 +197,18 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
       Res = TmpSeq;
   }
 
+  // If we have a 1 or 2 instruction sequence this is the best we can do. This
+  // will always be true for RV32 and will often be true for RV64.
+  if (Res.size() <= 2)
+    return Res;
+
+  assert(ActiveFeatures[RISCV::Feature64Bit] &&
+         "Expected RV32 to only need 2 instructions");
+
   // If the constant is positive we might be able to generate a shifted constant
   // with no leading zeros and use a final SRLI to restore them.
-  if (Val > 0 && Res.size() > 2) {
-    assert(ActiveFeatures[RISCV::Feature64Bit] &&
-           "Expected RV32 to only need 2 instructions");
+  if (Val > 0) {
+    assert(Res.size() > 2 && "Expected longer sequence");
     unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
     uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
     // Fill in the bits that will be shifted out with 1s. An example where this
@@ -244,9 +251,6 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
 
   // Perform optimization with BCLRI/BSETI in the Zbs extension.
   if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
-    assert(ActiveFeatures[RISCV::Feature64Bit] &&
-           "Expected RV32 to only need 2 instructions");
-
     // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
     //    call generateInstSeqImpl with Val|0x80000000 (which is expected be
     //    an int32), then emit (BCLRI r, 31).
@@ -299,8 +303,6 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
 
   // Perform optimization with SH*ADD in the Zba extension.
   if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
-    assert(ActiveFeatures[RISCV::Feature64Bit] &&
-           "Expected RV32 to only need 2 instructions");
     int64_t Div = 0;
     unsigned Opc = 0;
     RISCVMatInt::InstSeq TmpSeq;