[PATCH] D151449: [RISCV] Add DAG combine for CTTZ in the case of input 0

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11430
+
+  if (Op3.getOpcode() == ISD::TRUNCATE || Op3.getOpcode() == ISD::ZERO_EXTEND) {
+    CTTZ = Op3.getOperand(0);
----------------
```
SDValue CTTZ = N->getOperand(2);
if (CTTZ.getOpcode() == ISD::TRUNCATE || CTTZ.getOpcode() == ISD::ZERO_EXTEND)
  CTTZ = CTTZ.getOperand(0);
```


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11450
+  ISD::CondCode CCVal = cast<CondCodeSDNode>(Op1->getOperand(2))->get();
+  if (!ISD::isIntEqualitySetCC(CCVal))
+    return SDValue();
----------------
If we're requiring Op2 to be the null constant and Op3 to be the cttz then the only valid CC here is SETEQ. IsIntEquality checks for SETEQ or SETNE.

We should handle `X != 0 ? CTTZ : 0` as well


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449