[PATCH] D152223: [RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/half-select-fcmp.ll:877
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
----------------
Here's the regression, which looks easy to fix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152223/new/

https://reviews.llvm.org/D152223