[PATCH] D152223: [RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[Liao Chunyu via Phabricator via llvm-commits]

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Similar to x86. 
RISCV legalizing setgt to setlt, so this fold excludes setult,setlt,setule.
For setoeq, may not be the expected 
https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/float-br-fcmp.ll#L122


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152223

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-fcmp.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/double-select-fcmp.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-fcmp.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/float-select-fcmp.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/half-select-fcmp.ll
  llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

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