[PATCH] D152222: [RISCV] Fix the num of chain SDNode introduced in 9e0f9f113248093e737c4cf5450f0a3c2bcd90ba

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added a comment.

In D152222#4397984 <https://reviews.llvm.org/D152222#4397984>, @craig.topper wrote:

> In D152222#4397976 <https://reviews.llvm.org/D152222#4397976>, @zixuan-wu wrote:
>
>> In D152222#4397974 <https://reviews.llvm.org/D152222#4397974>, @craig.topper wrote:
>>
>>> When does a load and update node occur on RISC-v?
>>
>> It's actually less frequent because the standard extension does not have load update instruction. But XTHeadFMemIdx extension has load update instruction, so it appears in downstream.
>
> Should we even do the transform for an indexed load? Won’t we lose the update part of the load update?

It's not about the replacement of load update node, it's about VMV_V_X_VL node replacement. It just uses the data part of load update result. As the chain replacement, it just upgrades the chain from load update node to new vector load node because the new vector load node inserted after load update node in sequence order.


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  https://reviews.llvm.org/D152222/new/

https://reviews.llvm.org/D152222