[PATCH] D152222: [RISCV] Fix the num of chain SDNode introduced in 9e0f9f113248093e737c4cf5450f0a3c2bcd90ba

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D152222#4397976 <https://reviews.llvm.org/D152222#4397976>, @zixuan-wu wrote:

> In D152222#4397974 <https://reviews.llvm.org/D152222#4397974>, @craig.topper wrote:
>
>> When does a load and update node occur on RISC-v?
>
> It's actually less frequent because the standard extension does not have load update instruction. But XTHeadFMemIdx extension has load update instruction, so it appears in downstream.

Should we even do the transform for an indexed load?


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  https://reviews.llvm.org/D152222/new/

https://reviews.llvm.org/D152222