[PATCH] D152039: [RISCV] Remove uses of RISCVII::hasMergeOp from RISCVDAGToDAGISel.cpp

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 528618.
craig.topper added a comment.

Address Fraser's review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152039/new/

https://reviews.llvm.org/D152039

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp


Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3185,12 +3185,15 @@
   // Check that we're dropping the mask operand and any policy operand
   // when we transform to this unmasked pseudo. Additionally, if this
   // instruction is tail agnostic, the unmasked instruction should not have a
-  // merge op.
-  uint64_t TSFlags = TII.get(Opc).TSFlags;
-  assert((UseTUPseudo == RISCVII::hasMergeOp(TSFlags)) &&
-         RISCVII::hasDummyMaskOp(TSFlags) &&
+  // tied destination.
+#ifndef NDEBUG
+  const MCInstrDesc &MCID = TII.get(Opc);
+  uint64_t TSFlags = MCID.TSFlags;
+  bool HasTiedDest =
+      MCID.getOperandConstraint(MCID.getNumDefs(), MCOI::TIED_TO) == 0;
+  assert(UseTUPseudo == HasTiedDest && RISCVII::hasDummyMaskOp(TSFlags) &&
          "Unexpected pseudo to transform to");
-  (void)TSFlags;
+#endif
 
   SmallVector<SDValue, 8> Ops;
   // Skip the merge operand at index 0 if !UseTUPseudo.
@@ -3244,15 +3247,16 @@
     return false;
 
   unsigned TrueOpc = True.getMachineOpcode();
-
-  // Skip if True has merge operand.
-  uint64_t TrueTSFlags = TII->get(TrueOpc).TSFlags;
-  bool HasMergeOp = RISCVII::hasMergeOp(TrueTSFlags);
+  const MCInstrDesc &TrueMCID = TII->get(TrueOpc);
+  uint64_t TrueTSFlags = TrueMCID.TSFlags;
+  bool HasTiedDest =
+      TrueMCID.getNumOperands() >= 2 &&
+      TrueMCID.getOperandConstraint(TrueMCID.getNumDefs(), MCOI::TIED_TO) == 0;
 
   bool IsMasked = false;
   const RISCV::RISCVMaskedPseudoInfo *Info =
       RISCV::lookupMaskedIntrinsicByUnmaskedTA(TrueOpc);
-  if (!Info && HasMergeOp) {
+  if (!Info && HasTiedDest) {
     Info = RISCV::getMaskedPseudoInfo(TrueOpc);
     IsMasked = true;
   }
@@ -3260,7 +3264,7 @@
   if (!Info)
     return false;
 
-  if (HasMergeOp) {
+  if (HasTiedDest) {
     // The vmerge instruction must be TU.
     // FIXME: This could be relaxed, but we need to handle the policy for the
     // resulting op correctly.
@@ -3274,7 +3278,7 @@
   }
 
   if (IsMasked) {
-    assert(HasMergeOp && "Expected merge op");
+    assert(HasTiedDest && "Expected tied dest");
     // The vmerge instruction must be TU.
     if (IsTA)
       return false;
@@ -3333,10 +3337,14 @@
 
   SDLoc DL(N);
   unsigned MaskedOpc = Info->MaskedPseudo;
-  assert(RISCVII::hasVecPolicyOp(TII->get(MaskedOpc).TSFlags) &&
+#ifndef NDEBUG
+  const MCInstrDesc &MaskedMCID = TII->get(MaskedOpc);
+  assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) &&
          "Expected instructions with mask have policy operand.");
-  assert(RISCVII::hasMergeOp(TII->get(MaskedOpc).TSFlags) &&
-         "Expected instructions with mask have merge operand.");
+  assert(MaskedMCID.getOperandConstraint(MaskedMCID.getNumDefs(),
+                                         MCOI::TIED_TO) == 0 &&
+         "Expected instructions with mask have a tied dest.");
+#endif
 
   SmallVector<SDValue, 8> Ops;
   if (IsMasked) {
@@ -3346,7 +3354,7 @@
         CurDAG->getTargetConstant(Policy, DL, Subtarget->getXLenVT()));
     Ops.append(True->op_begin() + TrueVLIndex + 3, True->op_end());
   } else {
-    if (!HasMergeOp)
+    if (!HasTiedDest)
       Ops.push_back(False);
     Ops.append(True->op_begin(), True->op_begin() + TrueVLIndex);
     Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});


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