[PATCH] D151969: [RISCV] Add RISCVISD nodes for vfwadd/vfwsub.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/minor comment.

Note, I'm mostly trusting you have the tablegen bits right.  My review is really only meaningful for the C++ bits.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:417
 
-def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
-                                                SDTCisSameAs<0, 1>,
-                                                SDTCisInt<2>,
-                                                SDTCisSameNumEltsAs<1, 2>,
-                                                SDTCisOpSmallerThanOp<2, 1>,
-                                                SDTCisSameAs<0, 3>,
-                                                SDTCisSameNumEltsAs<1, 4>,
-                                                SDTCVecEltisVT<4, i1>,
-                                                SDTCisVT<5, XLenVT>]>;
-def riscv_vwadd_w_vl :  SDNode<"RISCVISD::VWADD_W_VL",  SDT_RISCVVWBinOpW_VL>;
-def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>;
-def riscv_vwsub_w_vl :  SDNode<"RISCVISD::VWSUB_W_VL",  SDT_RISCVVWBinOpW_VL>;
-def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>;
+def SDT_RISCVVWIntBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
+                                                   SDTCisSameAs<0, 1>,
----------------
Could you precommit the naming change so that this drops out of the diff?  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151969/new/

https://reviews.llvm.org/D151969