[llvm] 7a2b12b - [RISCV] Switch vwsll.v* instructions to use the VSHT_IV_V_X_I class instead of VALU_IV_V_X_I.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-05T09:24:50-07:00
New Revision: 7a2b12b05b39bce08987968270b43ca05d9a4836

URL: https://github.com/llvm/llvm-project/commit/7a2b12b05b39bce08987968270b43ca05d9a4836
DIFF: https://github.com/llvm/llvm-project/commit/7a2b12b05b39bce08987968270b43ca05d9a4836.diff

LOG: [RISCV] Switch vwsll.v* instructions to use the VSHT_IV_V_X_I class instead of VALU_IV_V_X_I.

This allows us to remove the uimm5 argument and changes the
scheduler class from ALU to Shift.

Ultimately we need a WShift scheduler class, but we need to scrub
all of the crypto instructions for scheduler classes so I'll leave
that for future work.

Reviewed By: 4vtomat, ego

Differential Revision: https://reviews.llvm.org/D152030

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index d89b0f8f22fd9..a6f3d154a2d2f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -442,14 +442,14 @@ multiclass VIndexLoadStore<list<int> EEWList> {
   }
 }
 
-multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
+multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
            Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
                   ReadVIALUV_WorstCase, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
            Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
                   ReadVIALUX_WorstCase, ReadVMask]>;
-  def I  : VALUVI<funct6, opcodestr # ".vi", optype>,
+  def I  : VALUVI<funct6, opcodestr # ".vi", simm5>,
            Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
                   ReadVMask]>;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index e5cc808d1fe1b..db8c90e834a1f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -139,7 +139,7 @@ let Predicates = [HasStdExtZvbb] in {
   defm VROL_V   : VALU_IV_V_X<"vrol", 0b010101>;
   defm VROR_V   : VROR_IV_V_X_I<"vror", 0b010100>;
   let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in
-  defm VWSLL_V  : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>;
+  defm VWSLL_V  : VSHT_IV_V_X_I<"vwsll", 0b110101>;
 } // Predicates = [HasStdExtZvbb]
 
 let Predicates = [HasStdExtZvbc] in {