[llvm] b28bc5f - [GlobalISel][X86] Add 128/256/512-bit vector and/or/xor test coverage
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 04:09:13 PDT 2023
Author: Simon Pilgrim
Date: 2023-06-05T12:08:22+01:00
New Revision: b28bc5f5ad7da086f65f260c32494922fd392f6b
URL: https://github.com/llvm/llvm-project/commit/b28bc5f5ad7da086f65f260c32494922fd392f6b
DIFF: https://github.com/llvm/llvm-project/commit/b28bc5f5ad7da086f65f260c32494922fd392f6b.diff
LOG: [GlobalISel][X86] Add 128/256/512-bit vector and/or/xor test coverage
Based off the legalize-add-v*.mir tests
Added:
llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-and-v256.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-and-v512.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-or-v128.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-or-v256.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-or-v512.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v128.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v256.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v512.mir
Modified:
Removed:
llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
################################################################################
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
deleted file mode 100644
index 32576e7fa18e8..0000000000000
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
+++ /dev/null
@@ -1,150 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
-
-# test vpand
-
----
-name: test_and_v8s32
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
- - { id: 2, class: _, preferred-register: '' }
-body: |
- bb.1:
-
- ; CHECK-LABEL: name: test_and_v8s32
- ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[AND]](<8 x s32>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
- %0:_(<8 x s32>) = IMPLICIT_DEF
- %1:_(<8 x s32>) = G_AND %0, %0
- %2:_(<8 x s32>) = COPY %1(<8 x s32>)
- RET 0, implicit %2
-...
----
-name: test_and_v4s64
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
- - { id: 2, class: _, preferred-register: '' }
-body: |
- bb.1:
-
- ; CHECK-LABEL: name: test_and_v4s64
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[AND]](<4 x s64>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
- %0:_(<4 x s64>) = IMPLICIT_DEF
- %1:_(<4 x s64>) = G_AND %0, %0
- %2:_(<4 x s64>) = COPY %1(<4 x s64>)
- RET 0, implicit %2
-...
----
-name: test_xor_v4s64
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
-body: |
- bb.1:
- ; CHECK-LABEL: name: test_xor_v4s64
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[XOR]](<4 x s64>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
- %0:_(<4 x s64>) = IMPLICIT_DEF
- %1:_(<4 x s64>) = G_XOR %0, %0
- %2:_(<4 x s64>) = COPY %1(<4 x s64>)
- RET 0, implicit %2
-
-...
----
-name: test_xor_v8s32
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
-body: |
- bb.1:
- ; CHECK-LABEL: name: test_xor_v8s32
- ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[XOR]](<8 x s32>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
- %0:_(<8 x s32>) = IMPLICIT_DEF
- %1:_(<8 x s32>) = G_XOR %0, %0
- %2:_(<8 x s32>) = COPY %1(<8 x s32>)
- RET 0, implicit %2
-
-...
----
-name: test_or_v4s64
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
-body: |
- bb.1:
- ; CHECK-LABEL: name: test_or_v4s64
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[OR]](<4 x s64>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
- %0:_(<4x s64>) = IMPLICIT_DEF
- %1:_(<4x s64>) = G_OR %0, %0
- %2:_(<4x s64>) = COPY %1(<4x s64>)
- RET 0, implicit %2
-
-...
----
-name: test_or_v8s32
-alignment: 16
-legalized: false
-regBankSelected: false
-registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
-body: |
- bb.1:
- ; CHECK-LABEL: name: test_or_v8s32
- ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[OR]](<8 x s32>)
- ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
- %0:_(<8x s32>) = IMPLICIT_DEF
- %1:_(<8x s32>) = G_OR %0, %0
- %2:_(<8x s32>) = COPY %1(<8x s32>)
- RET 0, implicit %2
-
-...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir
new file mode 100644
index 0000000000000..8de4e3c0e241f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir
@@ -0,0 +1,134 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
+
+--- |
+ define void @test_and_v16i8() {
+ %ret = and <16 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_and_v8i16() {
+ %ret = and <8 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_and_v4i32() {
+ %ret = and <4 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_and_v2i64() {
+ %ret = and <2 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_and_v16i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_and_v16i8
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[AND]](<16 x s8>)
+ ; CHECK-NEXT: RET 0
+ %0(<16 x s8>) = IMPLICIT_DEF
+ %1(<16 x s8>) = IMPLICIT_DEF
+ %2(<16 x s8>) = G_AND %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v8i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_and_v8i16
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[AND]](<8 x s16>)
+ ; CHECK-NEXT: RET 0
+ %0(<8 x s16>) = IMPLICIT_DEF
+ %1(<8 x s16>) = IMPLICIT_DEF
+ %2(<8 x s16>) = G_AND %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v4i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_and_v4i32
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[AND]](<4 x s32>)
+ ; CHECK-NEXT: RET 0
+ %0(<4 x s32>) = IMPLICIT_DEF
+ %1(<4 x s32>) = IMPLICIT_DEF
+ %2(<4 x s32>) = G_AND %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v2i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_and_v2i64
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[AND]](<2 x s64>)
+ ; CHECK-NEXT: RET 0
+ %0(<2 x s64>) = IMPLICIT_DEF
+ %1(<2 x s64>) = IMPLICIT_DEF
+ %2(<2 x s64>) = G_AND %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v256.mir
new file mode 100644
index 0000000000000..f21bec61c38cd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v256.mir
@@ -0,0 +1,182 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+
+--- |
+ define void @test_and_v32i8() {
+ %ret = and <32 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_and_v16i16() {
+ %ret = and <16 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_and_v8i32() {
+ %ret = and <8 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_and_v4i64() {
+ %ret = and <4 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_and_v32i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_and_v32i8
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
+ ; SSE-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[UV]], [[UV2]]
+ ; SSE-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[AND]](<16 x s8>), [[AND1]](<16 x s8>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_and_v32i8
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[AND]](<32 x s8>)
+ ; AVX-NEXT: RET 0
+ %0(<32 x s8>) = IMPLICIT_DEF
+ %1(<32 x s8>) = IMPLICIT_DEF
+ %2(<32 x s8>) = G_AND %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v16i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_and_v16i16
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
+ ; SSE-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[UV]], [[UV2]]
+ ; SSE-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[AND]](<8 x s16>), [[AND1]](<8 x s16>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_and_v16i16
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<16 x s16>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[AND]](<16 x s16>)
+ ; AVX-NEXT: RET 0
+ %0(<16 x s16>) = IMPLICIT_DEF
+ %1(<16 x s16>) = IMPLICIT_DEF
+ %2(<16 x s16>) = G_AND %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v8i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_and_v8i32
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
+ ; SSE-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[UV]], [[UV2]]
+ ; SSE-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[AND]](<4 x s32>), [[AND1]](<4 x s32>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_and_v8i32
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[AND]](<8 x s32>)
+ ; AVX-NEXT: RET 0
+ %0(<8 x s32>) = IMPLICIT_DEF
+ %1(<8 x s32>) = IMPLICIT_DEF
+ %2(<8 x s32>) = G_AND %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v4i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_and_v4i64
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
+ ; SSE-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[UV]], [[UV2]]
+ ; SSE-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[AND]](<2 x s64>), [[AND1]](<2 x s64>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_and_v4i64
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[AND]](<4 x s64>)
+ ; AVX-NEXT: RET 0
+ %0(<4 x s64>) = IMPLICIT_DEF
+ %1(<4 x s64>) = IMPLICIT_DEF
+ %2(<4 x s64>) = G_AND %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v512.mir
new file mode 100644
index 0000000000000..edac1496380d0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-v512.mir
@@ -0,0 +1,246 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+
+--- |
+ define void @test_and_v64i8() {
+ %ret = and <64 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_and_v32i16() {
+ %ret = and <32 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_and_v16i32() {
+ %ret = and <16 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_and_v8i64() {
+ %ret = and <8 x i64> undef, undef
+ ret void
+ }
+
+ define <64 x i8> @test_and_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
+ %ret = and <64 x i8> %arg1, %arg2
+ ret <64 x i8> %ret
+ }
+...
+---
+name: test_and_v64i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_and_v64i8
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV]], [[UV2]]
+ ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[AND]](<32 x s8>), [[AND1]](<32 x s8>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_and_v64i8
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[AND]](<64 x s8>)
+ ; AVX512-NEXT: RET 0
+ %0(<64 x s8>) = IMPLICIT_DEF
+ %1(<64 x s8>) = IMPLICIT_DEF
+ %2(<64 x s8>) = G_AND %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v32i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_and_v32i16
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV]], [[UV2]]
+ ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[AND]](<16 x s16>), [[AND1]](<16 x s16>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_and_v32i16
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<32 x s16>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[AND]](<32 x s16>)
+ ; AVX512-NEXT: RET 0
+ %0(<32 x s16>) = IMPLICIT_DEF
+ %1(<32 x s16>) = IMPLICIT_DEF
+ %2(<32 x s16>) = G_AND %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v16i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_and_v16i32
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV]], [[UV2]]
+ ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[AND]](<8 x s32>), [[AND1]](<8 x s32>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_and_v16i32
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[AND]](<16 x s32>)
+ ; AVX512-NEXT: RET 0
+ %0(<16 x s32>) = IMPLICIT_DEF
+ %1(<16 x s32>) = IMPLICIT_DEF
+ %2(<16 x s32>) = G_AND %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v8i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_and_v8i64
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV]], [[UV2]]
+ ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[AND]](<4 x s64>), [[AND1]](<4 x s64>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_and_v8i64
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<8 x s64>) = G_AND [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[AND]](<8 x s64>)
+ ; AVX512-NEXT: RET 0
+ %0(<8 x s64>) = IMPLICIT_DEF
+ %1(<8 x s64>) = IMPLICIT_DEF
+ %2(<8 x s64>) = G_AND %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_and_v64i8_2
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+#
+#
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-LABEL: name: test_and_v64i8_2
+ ; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY]], [[COPY2]]
+ ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY1]], [[COPY3]]
+ ; AVX-NEXT: $ymm0 = COPY [[AND]](<32 x s8>)
+ ; AVX-NEXT: $ymm1 = COPY [[AND1]](<32 x s8>)
+ ; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ ; AVX512-LABEL: name: test_and_v64i8_2
+ ; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
+ ; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
+ ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+ ; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[AND]](<64 x s8>)
+ ; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
+ ; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
+ ; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ %2(<32 x s8>) = COPY $ymm0
+ %3(<32 x s8>) = COPY $ymm1
+ %4(<32 x s8>) = COPY $ymm2
+ %5(<32 x s8>) = COPY $ymm3
+ %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
+ %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
+ %6(<64 x s8>) = G_AND %0, %1
+ %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
+ $ymm0 = COPY %7(<32 x s8>)
+ $ymm1 = COPY %8(<32 x s8>)
+ RET 0, implicit $ymm0, implicit $ymm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v128.mir
new file mode 100644
index 0000000000000..e5c6aa03fee3f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v128.mir
@@ -0,0 +1,134 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
+
+--- |
+ define void @test_or_v16i8() {
+ %ret = or <16 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_or_v8i16() {
+ %ret = or <8 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_or_v4i32() {
+ %ret = or <4 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_or_v2i64() {
+ %ret = or <2 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_or_v16i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_or_v16i8
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[OR]](<16 x s8>)
+ ; CHECK-NEXT: RET 0
+ %0(<16 x s8>) = IMPLICIT_DEF
+ %1(<16 x s8>) = IMPLICIT_DEF
+ %2(<16 x s8>) = G_OR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v8i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_or_v8i16
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[OR]](<8 x s16>)
+ ; CHECK-NEXT: RET 0
+ %0(<8 x s16>) = IMPLICIT_DEF
+ %1(<8 x s16>) = IMPLICIT_DEF
+ %2(<8 x s16>) = G_OR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v4i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_or_v4i32
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[OR]](<4 x s32>)
+ ; CHECK-NEXT: RET 0
+ %0(<4 x s32>) = IMPLICIT_DEF
+ %1(<4 x s32>) = IMPLICIT_DEF
+ %2(<4 x s32>) = G_OR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v2i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_or_v2i64
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[OR]](<2 x s64>)
+ ; CHECK-NEXT: RET 0
+ %0(<2 x s64>) = IMPLICIT_DEF
+ %1(<2 x s64>) = IMPLICIT_DEF
+ %2(<2 x s64>) = G_OR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v256.mir
new file mode 100644
index 0000000000000..8c189de61c5e0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v256.mir
@@ -0,0 +1,182 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+
+--- |
+ define void @test_or_v32i8() {
+ %ret = or <32 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_or_v16i16() {
+ %ret = or <16 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_or_v8i32() {
+ %ret = or <8 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_or_v4i64() {
+ %ret = or <4 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_or_v32i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_or_v32i8
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
+ ; SSE-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[OR]](<16 x s8>), [[OR1]](<16 x s8>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_or_v32i8
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)
+ ; AVX-NEXT: RET 0
+ %0(<32 x s8>) = IMPLICIT_DEF
+ %1(<32 x s8>) = IMPLICIT_DEF
+ %2(<32 x s8>) = G_OR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v16i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_or_v16i16
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
+ ; SSE-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[OR]](<8 x s16>), [[OR1]](<8 x s16>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_or_v16i16
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[OR]](<16 x s16>)
+ ; AVX-NEXT: RET 0
+ %0(<16 x s16>) = IMPLICIT_DEF
+ %1(<16 x s16>) = IMPLICIT_DEF
+ %2(<16 x s16>) = G_OR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v8i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_or_v8i32
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
+ ; SSE-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[OR]](<4 x s32>), [[OR1]](<4 x s32>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_or_v8i32
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[OR]](<8 x s32>)
+ ; AVX-NEXT: RET 0
+ %0(<8 x s32>) = IMPLICIT_DEF
+ %1(<8 x s32>) = IMPLICIT_DEF
+ %2(<8 x s32>) = G_OR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v4i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_or_v4i64
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
+ ; SSE-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[OR]](<2 x s64>), [[OR1]](<2 x s64>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_or_v4i64
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[OR]](<4 x s64>)
+ ; AVX-NEXT: RET 0
+ %0(<4 x s64>) = IMPLICIT_DEF
+ %1(<4 x s64>) = IMPLICIT_DEF
+ %2(<4 x s64>) = G_OR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v512.mir
new file mode 100644
index 0000000000000..1647535a11bc6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-v512.mir
@@ -0,0 +1,246 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+
+--- |
+ define void @test_or_v64i8() {
+ %ret = or <64 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_or_v32i16() {
+ %ret = or <32 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_or_v16i32() {
+ %ret = or <16 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_or_v8i64() {
+ %ret = or <8 x i64> undef, undef
+ ret void
+ }
+
+ define <64 x i8> @test_or_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
+ %ret = or <64 x i8> %arg1, %arg2
+ ret <64 x i8> %ret
+ }
+...
+---
+name: test_or_v64i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_or_v64i8
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[OR]](<32 x s8>), [[OR1]](<32 x s8>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_or_v64i8
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[OR]](<64 x s8>)
+ ; AVX512-NEXT: RET 0
+ %0(<64 x s8>) = IMPLICIT_DEF
+ %1(<64 x s8>) = IMPLICIT_DEF
+ %2(<64 x s8>) = G_OR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v32i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_or_v32i16
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[OR]](<16 x s16>), [[OR1]](<16 x s16>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_or_v32i16
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<32 x s16>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[OR]](<32 x s16>)
+ ; AVX512-NEXT: RET 0
+ %0(<32 x s16>) = IMPLICIT_DEF
+ %1(<32 x s16>) = IMPLICIT_DEF
+ %2(<32 x s16>) = G_OR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v16i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_or_v16i32
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[OR]](<8 x s32>), [[OR1]](<8 x s32>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_or_v16i32
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[OR]](<16 x s32>)
+ ; AVX512-NEXT: RET 0
+ %0(<16 x s32>) = IMPLICIT_DEF
+ %1(<16 x s32>) = IMPLICIT_DEF
+ %2(<16 x s32>) = G_OR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v8i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_or_v8i64
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[OR]](<4 x s64>), [[OR1]](<4 x s64>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_or_v8i64
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<8 x s64>) = G_OR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[OR]](<8 x s64>)
+ ; AVX512-NEXT: RET 0
+ %0(<8 x s64>) = IMPLICIT_DEF
+ %1(<8 x s64>) = IMPLICIT_DEF
+ %2(<8 x s64>) = G_OR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_or_v64i8_2
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+#
+#
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-LABEL: name: test_or_v64i8_2
+ ; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY]], [[COPY2]]
+ ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY1]], [[COPY3]]
+ ; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)
+ ; AVX-NEXT: $ymm1 = COPY [[OR1]](<32 x s8>)
+ ; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ ; AVX512-LABEL: name: test_or_v64i8_2
+ ; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
+ ; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
+ ; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+ ; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[OR]](<64 x s8>)
+ ; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
+ ; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
+ ; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ %2(<32 x s8>) = COPY $ymm0
+ %3(<32 x s8>) = COPY $ymm1
+ %4(<32 x s8>) = COPY $ymm2
+ %5(<32 x s8>) = COPY $ymm3
+ %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
+ %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
+ %6(<64 x s8>) = G_OR %0, %1
+ %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
+ $ymm0 = COPY %7(<32 x s8>)
+ $ymm1 = COPY %8(<32 x s8>)
+ RET 0, implicit $ymm0, implicit $ymm1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v128.mir
new file mode 100644
index 0000000000000..33e6e66cee107
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v128.mir
@@ -0,0 +1,134 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
+
+--- |
+ define void @test_xor_v16i8() {
+ %ret = xor <16 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v8i16() {
+ %ret = xor <8 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v4i32() {
+ %ret = xor <4 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v2i64() {
+ %ret = xor <2 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_xor_v16i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_xor_v16i8
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<16 x s8>)
+ ; CHECK-NEXT: RET 0
+ %0(<16 x s8>) = IMPLICIT_DEF
+ %1(<16 x s8>) = IMPLICIT_DEF
+ %2(<16 x s8>) = G_XOR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v8i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_xor_v8i16
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<8 x s16>)
+ ; CHECK-NEXT: RET 0
+ %0(<8 x s16>) = IMPLICIT_DEF
+ %1(<8 x s16>) = IMPLICIT_DEF
+ %2(<8 x s16>) = G_XOR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v4i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_xor_v4i32
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<4 x s32>)
+ ; CHECK-NEXT: RET 0
+ %0(<4 x s32>) = IMPLICIT_DEF
+ %1(<4 x s32>) = IMPLICIT_DEF
+ %2(<4 x s32>) = G_XOR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v2i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $xmm0, $xmm1
+
+ ; CHECK-LABEL: name: test_xor_v2i64
+ ; CHECK: liveins: $xmm0, $xmm1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $xmm0 = COPY [[XOR]](<2 x s64>)
+ ; CHECK-NEXT: RET 0
+ %0(<2 x s64>) = IMPLICIT_DEF
+ %1(<2 x s64>) = IMPLICIT_DEF
+ %2(<2 x s64>) = G_XOR %0, %1
+ $xmm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v256.mir
new file mode 100644
index 0000000000000..f783d0c64ffba
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v256.mir
@@ -0,0 +1,182 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+
+--- |
+ define void @test_xor_v32i8() {
+ %ret = xor <32 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v16i16() {
+ %ret = xor <16 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v8i32() {
+ %ret = xor <8 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v4i64() {
+ %ret = xor <4 x i64> undef, undef
+ ret void
+ }
+...
+---
+name: test_xor_v32i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_xor_v32i8
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
+ ; SSE-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s8>) = G_XOR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[XOR]](<16 x s8>), [[XOR1]](<16 x s8>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_xor_v32i8
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[XOR]](<32 x s8>)
+ ; AVX-NEXT: RET 0
+ %0(<32 x s8>) = IMPLICIT_DEF
+ %1(<32 x s8>) = IMPLICIT_DEF
+ %2(<32 x s8>) = G_XOR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v16i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_xor_v16i16
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
+ ; SSE-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s16>) = G_XOR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[XOR]](<8 x s16>), [[XOR1]](<8 x s16>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_xor_v16i16
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<16 x s16>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[XOR]](<16 x s16>)
+ ; AVX-NEXT: RET 0
+ %0(<16 x s16>) = IMPLICIT_DEF
+ %1(<16 x s16>) = IMPLICIT_DEF
+ %2(<16 x s16>) = G_XOR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v8i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_xor_v8i32
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
+ ; SSE-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<4 x s32>) = G_XOR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[XOR]](<4 x s32>), [[XOR1]](<4 x s32>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_xor_v8i32
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[XOR]](<8 x s32>)
+ ; AVX-NEXT: RET 0
+ %0(<8 x s32>) = IMPLICIT_DEF
+ %1(<8 x s32>) = IMPLICIT_DEF
+ %2(<8 x s32>) = G_XOR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v4i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1
+
+ ; SSE-LABEL: name: test_xor_v4i64
+ ; SSE: liveins: $ymm0, $ymm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
+ ; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
+ ; SSE-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[UV]], [[UV2]]
+ ; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[UV1]], [[UV3]]
+ ; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[XOR]](<2 x s64>), [[XOR1]](<2 x s64>)
+ ; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
+ ; SSE-NEXT: RET 0
+ ; AVX-LABEL: name: test_xor_v4i64
+ ; AVX: liveins: $ymm0, $ymm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX-NEXT: $ymm0 = COPY [[XOR]](<4 x s64>)
+ ; AVX-NEXT: RET 0
+ %0(<4 x s64>) = IMPLICIT_DEF
+ %1(<4 x s64>) = IMPLICIT_DEF
+ %2(<4 x s64>) = G_XOR %0, %1
+ $ymm0 = COPY %2
+ RET 0
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v512.mir
new file mode 100644
index 0000000000000..9f5b1ec3b309c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v512.mir
@@ -0,0 +1,246 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
+
+--- |
+ define void @test_xor_v64i8() {
+ %ret = xor <64 x i8> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v32i16() {
+ %ret = xor <32 x i16> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v16i32() {
+ %ret = xor <16 x i32> undef, undef
+ ret void
+ }
+
+ define void @test_xor_v8i64() {
+ %ret = xor <8 x i64> undef, undef
+ ret void
+ }
+
+ define <64 x i8> @test_xor_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
+ %ret = xor <64 x i8> %arg1, %arg2
+ ret <64 x i8> %ret
+ }
+...
+---
+name: test_xor_v64i8
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_xor_v64i8
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[XOR]](<32 x s8>), [[XOR1]](<32 x s8>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_xor_v64i8
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<64 x s8>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[XOR]](<64 x s8>)
+ ; AVX512-NEXT: RET 0
+ %0(<64 x s8>) = IMPLICIT_DEF
+ %1(<64 x s8>) = IMPLICIT_DEF
+ %2(<64 x s8>) = G_XOR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v32i16
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_xor_v32i16
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<16 x s16>) = G_XOR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s16>) = G_XOR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[XOR]](<16 x s16>), [[XOR1]](<16 x s16>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_xor_v32i16
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<32 x s16>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[XOR]](<32 x s16>)
+ ; AVX512-NEXT: RET 0
+ %0(<32 x s16>) = IMPLICIT_DEF
+ %1(<32 x s16>) = IMPLICIT_DEF
+ %2(<32 x s16>) = G_XOR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v16i32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_xor_v16i32
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s32>) = G_XOR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[XOR]](<8 x s32>), [[XOR1]](<8 x s32>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_xor_v16i32
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<16 x s32>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[XOR]](<16 x s32>)
+ ; AVX512-NEXT: RET 0
+ %0(<16 x s32>) = IMPLICIT_DEF
+ %1(<16 x s32>) = IMPLICIT_DEF
+ %2(<16 x s32>) = G_XOR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v8i64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $zmm0, $zmm1
+
+ ; AVX-LABEL: name: test_xor_v8i64
+ ; AVX: liveins: $zmm0, $zmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
+ ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[UV]], [[UV2]]
+ ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<4 x s64>) = G_XOR [[UV1]], [[UV3]]
+ ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[XOR]](<4 x s64>), [[XOR1]](<4 x s64>)
+ ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
+ ; AVX-NEXT: RET 0
+ ; AVX512-LABEL: name: test_xor_v8i64
+ ; AVX512: liveins: $zmm0, $zmm1
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<8 x s64>) = G_XOR [[DEF]], [[DEF1]]
+ ; AVX512-NEXT: $zmm0 = COPY [[XOR]](<8 x s64>)
+ ; AVX512-NEXT: RET 0
+ %0(<8 x s64>) = IMPLICIT_DEF
+ %1(<8 x s64>) = IMPLICIT_DEF
+ %2(<8 x s64>) = G_XOR %0, %1
+ $zmm0 = COPY %2
+ RET 0
+...
+---
+name: test_xor_v64i8_2
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+#
+#
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-LABEL: name: test_xor_v64i8_2
+ ; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[COPY]], [[COPY2]]
+ ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s8>) = G_XOR [[COPY1]], [[COPY3]]
+ ; AVX-NEXT: $ymm0 = COPY [[XOR]](<32 x s8>)
+ ; AVX-NEXT: $ymm1 = COPY [[XOR1]](<32 x s8>)
+ ; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ ; AVX512-LABEL: name: test_xor_v64i8_2
+ ; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
+ ; AVX512-NEXT: {{ $}}
+ ; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
+ ; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
+ ; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
+ ; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
+ ; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
+ ; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
+ ; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<64 x s8>) = G_XOR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+ ; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[XOR]](<64 x s8>)
+ ; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
+ ; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
+ ; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ %2(<32 x s8>) = COPY $ymm0
+ %3(<32 x s8>) = COPY $ymm1
+ %4(<32 x s8>) = COPY $ymm2
+ %5(<32 x s8>) = COPY $ymm3
+ %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
+ %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
+ %6(<64 x s8>) = G_XOR %0, %1
+ %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
+ $ymm0 = COPY %7(<32 x s8>)
+ $ymm1 = COPY %8(<32 x s8>)
+ RET 0, implicit $ymm0, implicit $ymm1
+...
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