[llvm] dbd3695 - [GlobalISel][X86] Add illegal types and 32-bit target scalar and/or/xor test coverage
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 04:09:11 PDT 2023
Author: Simon Pilgrim
Date: 2023-06-05T12:08:22+01:00
New Revision: dbd36950921bde92e551d514052c77c631c33c7d
URL: https://github.com/llvm/llvm-project/commit/dbd36950921bde92e551d514052c77c631c33c7d
DIFF: https://github.com/llvm/llvm-project/commit/dbd36950921bde92e551d514052c77c631c33c7d.diff
LOG: [GlobalISel][X86] Add illegal types and 32-bit target scalar and/or/xor test coverage
Based off the legalize-add.mir tests
Added:
Modified:
llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
index 1f09e4639df59..c547af58e1204 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
+# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
- define i1 @test_and_i1() {
- %ret = and i1 undef, undef
- ret i1 %ret
- }
- define i8 @test_and_i8() {
- %ret = and i8 undef, undef
- ret i8 %ret
- }
-
- define i16 @test_and_i16() {
- %ret = and i16 undef, undef
- ret i16 %ret
- }
-
- define i32 @test_and_i32() {
- %ret = and i32 undef, undef
- ret i32 %ret
- }
-
- define i64 @test_and_i64() {
- %ret = and i64 undef, undef
- ret i64 %ret
- }
+ define void @test_and_i1() { ret void}
+ define void @test_and_i8() { ret void }
+ define void @test_and_i16() { ret void }
+ define void @test_and_i27() { ret void }
+ define void @test_and_i32() { ret void }
+ define void @test_and_i42() { ret void }
+ define void @test_and_i64() { ret void }
...
---
@@ -39,15 +24,14 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
-
; CHECK-LABEL: name: test_and_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
- ; CHECK: $eax = COPY [[ANYEXT]](s32)
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_AND %1, %1
@@ -63,22 +47,22 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i8
- ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[DEF]], [[DEF]]
- ; CHECK: $al = COPY [[AND]](s8)
- ; CHECK: RET 0, implicit $al
- %0(s8) = IMPLICIT_DEF
- %1(s8) = G_AND %0, %0
- $al = COPY %1(s8)
- RET 0, implicit $al
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s8) = G_AND %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_and_i16
@@ -86,24 +70,47 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i16
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[DEF]], [[DEF]]
- ; CHECK: $ax = COPY [[AND]](s16)
- ; CHECK: RET 0, implicit $ax
- %0(s16) = IMPLICIT_DEF
- %1(s16) = G_AND %0, %0
- $ax = COPY %1(s16)
- RET 0, implicit $ax
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s16) = G_AND %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
+...
+---
+name: test_and_i27
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i27
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $eax = COPY [[AND]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s27) = G_TRUNC %0(s32)
+ %2(s27) = G_AND %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_and_i32
@@ -111,24 +118,54 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF]]
- ; CHECK: $eax = COPY [[AND]](s32)
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $eax = COPY [[AND]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
- %1(s32) = G_AND %0, %0
- $eax = COPY %1(s32)
- RET 0, implicit $eax
-
+ %1(s32) = IMPLICIT_DEF
+ %2(s32) = G_AND %0, %1
+ $eax = COPY %2
+ RET 0
+...
+---
+name: test_and_i42
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_and_i42
+ ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY]]
+ ; X64-NEXT: $rax = COPY [[AND]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_and_i42
+ ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
+ ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
+ %0(s64) = COPY $rdx
+ %1(s42) = G_TRUNC %0(s64)
+ %2(s42) = G_AND %1, %1
+ %3:_(s64) = G_ANYEXT %2
+ $rax = COPY %3
+ RET 0
...
---
name: test_and_i64
@@ -136,22 +173,30 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
- ; CHECK-LABEL: name: test_and_i64
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
- ; CHECK: $rax = COPY [[AND]](s64)
- ; CHECK: RET 0, implicit $rax
+ ; X64-LABEL: name: test_and_i64
+ ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF1]]
+ ; X64-NEXT: $rax = COPY [[AND]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_and_i64
+ ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
+ ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
- %1(s64) = G_AND %0, %0
- $rax = COPY %1(s64)
- RET 0, implicit $rax
-
+ %1(s64) = IMPLICIT_DEF
+ %2(s64) = G_AND %0, %1
+ $rax = COPY %2
+ RET 0
...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
index d51e032aef18f..58c21f0310b36 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
+# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
- define i1 @test_or_i1() {
- %ret = or i1 undef, undef
- ret i1 %ret
- }
- define i8 @test_or_i8() {
- %ret = or i8 undef, undef
- ret i8 %ret
- }
-
- define i16 @test_or_i16() {
- %ret = or i16 undef, undef
- ret i16 %ret
- }
-
- define i32 @test_or_i32() {
- %ret = or i32 undef, undef
- ret i32 %ret
- }
-
- define i64 @test_or_i64() {
- %ret = or i64 undef, undef
- ret i64 %ret
- }
+ define void @test_or_i1() { ret void}
+ define void @test_or_i8() { ret void }
+ define void @test_or_i16() { ret void }
+ define void @test_or_i27() { ret void }
+ define void @test_or_i32() { ret void }
+ define void @test_or_i42() { ret void }
+ define void @test_or_i64() { ret void }
...
---
@@ -39,22 +24,19 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
-
; CHECK-LABEL: name: test_or_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[OR]], [[C]]
- ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_OR %1, %1
- %3:_(p0) = G_IMPLICIT_DEF
- G_STORE %2, %3 :: (store (s1))
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
RET 0
...
---
@@ -65,22 +47,22 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i8
- ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
- ; CHECK: $al = COPY [[OR]](s8)
- ; CHECK: RET 0, implicit $al
- %0(s8) = IMPLICIT_DEF
- %1(s8) = G_OR %0, %0
- $al = COPY %1(s8)
- RET 0, implicit $al
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s8) = G_OR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_or_i16
@@ -88,24 +70,47 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i16
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
- ; CHECK: $ax = COPY [[OR]](s16)
- ; CHECK: RET 0, implicit $ax
- %0(s16) = IMPLICIT_DEF
- %1(s16) = G_OR %0, %0
- $ax = COPY %1(s16)
- RET 0, implicit $ax
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s16) = G_OR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
+...
+---
+name: test_or_i27
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i27
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $eax = COPY [[OR]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s27) = G_TRUNC %0(s32)
+ %2(s27) = G_OR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_or_i32
@@ -113,24 +118,54 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
- ; CHECK: $eax = COPY [[OR]](s32)
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $eax = COPY [[OR]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
- %1(s32) = G_OR %0, %0
- $eax = COPY %1(s32)
- RET 0, implicit $eax
-
+ %1(s32) = IMPLICIT_DEF
+ %2(s32) = G_OR %0, %1
+ $eax = COPY %2
+ RET 0
+...
+---
+name: test_or_i42
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_or_i42
+ ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY]]
+ ; X64-NEXT: $rax = COPY [[OR]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_or_i42
+ ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]]
+ ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
+ %0(s64) = COPY $rdx
+ %1(s42) = G_TRUNC %0(s64)
+ %2(s42) = G_OR %1, %1
+ %3:_(s64) = G_ANYEXT %2
+ $rax = COPY %3
+ RET 0
...
---
name: test_or_i64
@@ -138,22 +173,30 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
- ; CHECK-LABEL: name: test_or_i64
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
- ; CHECK: $rax = COPY [[OR]](s64)
- ; CHECK: RET 0, implicit $rax
+ ; X64-LABEL: name: test_or_i64
+ ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF1]]
+ ; X64-NEXT: $rax = COPY [[OR]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_or_i64
+ ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]]
+ ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
- %1(s64) = G_OR %0, %0
- $rax = COPY %1(s64)
- RET 0, implicit $rax
-
+ %1(s64) = IMPLICIT_DEF
+ %2(s64) = G_OR %0, %1
+ $rax = COPY %2
+ RET 0
...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
index d2adaaa37d64f..dd1d215276788 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
+# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
- define i1 @test_xor_i1() {
- %ret = xor i1 undef, undef
- ret i1 %ret
- }
- define i8 @test_xor_i8() {
- %ret = xor i8 undef, undef
- ret i8 %ret
- }
-
- define i16 @test_xor_i16() {
- %ret = xor i16 undef, undef
- ret i16 %ret
- }
-
- define i32 @test_xor_i32() {
- %ret = xor i32 undef, undef
- ret i32 %ret
- }
-
- define i64 @test_xor_i64() {
- %ret = xor i64 undef, undef
- ret i64 %ret
- }
+ define void @test_xor_i1() { ret void}
+ define void @test_xor_i8() { ret void }
+ define void @test_xor_i16() { ret void }
+ define void @test_xor_i27() { ret void }
+ define void @test_xor_i32() { ret void }
+ define void @test_xor_i42() { ret void }
+ define void @test_xor_i64() { ret void }
...
---
@@ -39,18 +24,19 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
-
; CHECK-LABEL: name: test_xor_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_XOR %1, %1
- %3:_(p0) = G_IMPLICIT_DEF
- G_STORE %2, %3 ::(store (s1))
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
RET 0
...
---
@@ -61,22 +47,22 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i8
- ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
- ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: $al = COPY [[XOR]](s8)
- ; CHECK: RET 0, implicit $al
- %0(s8) = IMPLICIT_DEF
- %1(s8) = G_XOR %0, %0
- $al = COPY %1(s8)
- RET 0, implicit $al
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s8) = G_TRUNC %0(s32)
+ %2(s8) = G_XOR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_xor_i16
@@ -84,24 +70,47 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i16
- ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
- ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: $ax = COPY [[XOR]](s16)
- ; CHECK: RET 0, implicit $ax
- %0(s16) = IMPLICIT_DEF
- %1(s16) = G_XOR %0, %0
- $ax = COPY %1(s16)
- RET 0, implicit $ax
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[TRUNC]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s16)
+ ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s16) = G_TRUNC %0(s32)
+ %2(s16) = G_XOR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
+...
+---
+name: test_xor_i27
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i27
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $eax = COPY [[XOR]](s32)
+ ; CHECK-NEXT: RET 0
+ %0(s32) = COPY $edx
+ %1(s27) = G_TRUNC %0(s32)
+ %2(s27) = G_XOR %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ $eax = COPY %3
+ RET 0
...
---
name: test_xor_i32
@@ -109,24 +118,54 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: $eax = COPY [[XOR]](s32)
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF1]]
+ ; CHECK-NEXT: $eax = COPY [[XOR]](s32)
+ ; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
- %1(s32) = G_XOR %0, %0
- $eax = COPY %1(s32)
- RET 0, implicit $eax
-
+ %1(s32) = IMPLICIT_DEF
+ %2(s32) = G_XOR %0, %1
+ $eax = COPY %2
+ RET 0
+...
+---
+name: test_xor_i42
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_xor_i42
+ ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X64-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY]]
+ ; X64-NEXT: $rax = COPY [[XOR]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_xor_i42
+ ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV2]]
+ ; X86-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[XOR]](s32), [[XOR1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
+ %0(s64) = COPY $rdx
+ %1(s42) = G_TRUNC %0(s64)
+ %2(s42) = G_XOR %1, %1
+ %3:_(s64) = G_ANYEXT %2
+ $rax = COPY %3
+ RET 0
...
---
name: test_xor_i64
@@ -134,22 +173,30 @@ alignment: 16
legalized: false
regBankSelected: false
registers:
- - { id: 0, class: _, preferred-register: '' }
- - { id: 1, class: _, preferred-register: '' }
-liveins:
-fixedStack:
-stack:
-constants:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
- ; CHECK-LABEL: name: test_xor_i64
- ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
- ; CHECK: $rax = COPY [[XOR]](s64)
- ; CHECK: RET 0, implicit $rax
+ ; X64-LABEL: name: test_xor_i64
+ ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF1]]
+ ; X64-NEXT: $rax = COPY [[XOR]](s64)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_xor_i64
+ ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X86-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV2]]
+ ; X86-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[UV3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[XOR]](s32), [[XOR1]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
- %1(s64) = G_XOR %0, %0
- $rax = COPY %1(s64)
- RET 0, implicit $rax
-
+ %1(s64) = IMPLICIT_DEF
+ %2(s64) = G_XOR %0, %1
+ $rax = COPY %2
+ RET 0
...
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