[PATCH] D152120: [M68k][MC] Add support for 32 bit register-register multiply/divide

[Ian D. Scott via Phabricator via llvm-commits]

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Previously when targeting 68020+, instruction selection attempted to
emit a 32-bit register-register multiplication, but failed at
instruction selection. With this, it succeeds.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152120

Files:
  llvm/lib/Target/M68k/M68kInstrArithmetic.td
  llvm/test/MC/M68k/Arith/Classes/MxDiMu.s


Index: llvm/test/MC/M68k/Arith/Classes/MxDiMu.s
===================================================================
--- llvm/test/MC/M68k/Arith/Classes/MxDiMu.s
+++ llvm/test/MC/M68k/Arith/Classes/MxDiMu.s
@@ -12,6 +12,12 @@
 ; CHECK:      divu  #-1, %d0
 ; CHECK-SAME: encoding: [0x80,0xfc,0xff,0xff]
 divu	#-1, %d0
+; CHECK:	divs.l	%d1, %d0
+; CHECK-SAME:	encoding: [0x4c,0x41,0x08,0x00]
+divs.l	%d1, %d0
+; CHECK:	divu.l	%d1, %d0
+; CHECK-SAME:	encoding: [0x4c,0x41,0x00,0x00]
+divu.l	%d1, %d0
 ; CHECK:      muls  %d1, %d0
 ; CHECK-SAME: encoding: [0xc1,0xc1]
 muls	%d1, %d0
@@ -24,3 +30,9 @@
 ; CHECK:      mulu  #-1, %d0
 ; CHECK-SAME: encoding: [0xc0,0xfc,0xff,0xff]
 mulu	#-1, %d0
+; CHECK:      muls.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x01,0x08,0x00]
+muls.l	%d1, %d0
+; CHECK:      mulu.l  %d1, %d0
+; CHECK-SAME: encoding: [0x4c,0x01,0x00,0x00]
+mulu.l	%d1, %d0
Index: llvm/lib/Target/M68k/M68kInstrArithmetic.td
===================================================================
--- llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -589,6 +589,22 @@
   );
 }
 
+// $dreg <- $dreg op $dreg
+class MxDiMuOp_DD_Long<string MN, bits<10> CMD, bit SIGNED = false>
+    : MxInst<(outs MxDRD32:$dst), (ins MxDRD32:$src, MxDRD32:$opd), MN#"\t$opd, $dst", []> {
+  let Inst = (ascend
+    (descend CMD,
+      /*MODE*/0b000, /*REGISTER*/(operand "$opd", 3)),
+    (descend 0b0,
+      // REGISTER
+      (operand "$dst", 3),
+      !if(SIGNED, 0b1, 0b0),
+      /*SIZE*/0b0, 0b0000000,
+      // Dr REGISTER
+      0b000)
+  );
+}
+
 // $reg <- $reg op $imm
 class MxDiMuOp_DI<string MN, bits<4> CMD, bit SIGNED = false,
                   MxOperand DST, MxOperand OPD>
@@ -618,6 +634,9 @@
 
 defm DIV : MxDiMuOp<"div", 0x8>;
 
+def "SDIVd32d32" : MxDiMuOp_DD_Long<"divs.l", 0x131, /*SIGNED*/true>;
+def "UDIVd32d32" : MxDiMuOp_DD_Long<"divu.l", 0x131, /*SIGNED*/false>;
+
 // This is used to cast immediates to 16-bits for operations which don't
 // support smaller immediate sizes.
 def as_i16imm : SDNodeXForm<imm, [{
@@ -667,6 +686,12 @@
              MxSubRegIndex16Lo)>;
 
 
+// RR i32
+def : Pat<(sdiv i32:$dst, i32:$opd), (SDIVd32d32 $dst, $opd)>;
+
+def : Pat<(udiv i32:$dst, i32:$opd), (UDIVd32d32 $dst, $opd)>;
+
+
 // RI i8
 def : Pat<(sdiv i8:$dst, MximmSExt8:$opd),
           (EXTRACT_SUBREG
@@ -712,6 +737,9 @@
 
 defm MUL : MxDiMuOp<"mul", 0xC, 1>;
 
+def "SMULd32d32" : MxDiMuOp_DD_Long<"muls.l", 0x130, /*SIGNED*/true>;
+def "UMULd32d32" : MxDiMuOp_DD_Long<"mulu.l", 0x130, /*SIGNED*/false>;
+
 // RR
 def : Pat<(mul i16:$dst, i16:$opd),
           (EXTRACT_SUBREG
@@ -728,6 +756,8 @@
             (LSR32di (LSR32di (UMULd32d16 (MOVXd32d16 $dst), $opd), 8), 8),
              MxSubRegIndex16Lo)>;
 
+def : Pat<(mul i32:$dst, i32:$opd), (SMULd32d32 $dst, $opd)>;
+
 
 // RI
 def : Pat<(mul i16:$dst, MximmSExt16:$opd),


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