[llvm] 6effec1 - [GlobalIsel][X86] Move G_PTRTOINT/G_INTTOPTR legalization before legacy handling and merge 32-bit/64-bit handling

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sun Jun 4 07:22:06 PDT 2023


Author: Simon Pilgrim
Date: 2023-06-04T15:21:42+01:00
New Revision: 6effec1a5058ccd19ebea520b0956732075cd8a7

URL: https://github.com/llvm/llvm-project/commit/6effec1a5058ccd19ebea520b0956732075cd8a7
DIFF: https://github.com/llvm/llvm-project/commit/6effec1a5058ccd19ebea520b0956732075cd8a7.diff

LOG: [GlobalIsel][X86] Move G_PTRTOINT/G_INTTOPTR legalization before legacy handling and merge 32-bit/64-bit handling

I've kept the legalForCartesianProduct call, but this requires us to maintain 32-bit/64-bit integer lists - we might want to just use legalIf and perform the type pair set matching manually.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86LegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index b859415ff7a9e..ec84c57851636 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -71,6 +71,8 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
   bool HasDQI = Subtarget.hasAVX512() && Subtarget.hasDQI();
   bool HasBWI = Subtarget.hasAVX512() && Subtarget.hasBWI();
 
+  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
+  const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
@@ -227,6 +229,17 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
       .widenScalarToNextPow2(1, /*Min=*/16)
       .clampScalar(1, s16, sMaxScalar);
 
+  // pointer handling
+  const std::initializer_list<LLT> PtrTypes32 = {s1, s8, s16, s32};
+  const std::initializer_list<LLT> PtrTypes64 = {s1, s8, s16, s32, s64};
+
+  getActionDefinitionsBuilder(G_PTRTOINT)
+      .legalForCartesianProduct(Is64Bit ? PtrTypes64 : PtrTypes32, {p0})
+      .maxScalar(0, sMaxScalar)
+      .widenScalarToNextPow2(0, /*Min*/ 8);
+
+  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, sMaxScalar}});
+
   setLegalizerInfo32bit();
   setLegalizerInfo64bit();
   setLegalizerInfoSSE1();
@@ -302,12 +315,6 @@ void X86LegalizerInfo::setLegalizerInfo32bit() {
   LegacyInfo.setAction({G_PTR_ADD, 1, s32}, LegacyLegalizeActions::Legal);
 
   if (!Subtarget.is64Bit()) {
-    getActionDefinitionsBuilder(G_PTRTOINT)
-        .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
-        .maxScalar(0, s32)
-        .widenScalarToNextPow2(0, /*Min*/ 8);
-    getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
-
     // Comparison
     getActionDefinitionsBuilder(G_ICMP)
         .legalForCartesianProduct({s8}, {s8, s16, s32, p0})
@@ -349,7 +356,6 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
     return;
 
   const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
-  const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
@@ -370,11 +376,6 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
 
   // Pointer-handling
   LegacyInfo.setAction({G_PTR_ADD, 1, s64}, LegacyLegalizeActions::Legal);
-  getActionDefinitionsBuilder(G_PTRTOINT)
-      .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
-      .maxScalar(0, s64)
-      .widenScalarToNextPow2(0, /*Min*/ 8);
-  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s64}});
 
   // Constants
   LegacyInfo.setAction({TargetOpcode::G_CONSTANT, s64},


        


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