[llvm] 6595cb1 - [m68k] Implement BSR Instruction
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 3 04:10:21 PDT 2023
Author: Sheng
Date: 2023-06-03T19:09:47+08:00
New Revision: 6595cb1dbb4074d3dcf5dd4a11ec89aee530b135
URL: https://github.com/llvm/llvm-project/commit/6595cb1dbb4074d3dcf5dd4a11ec89aee530b135
DIFF: https://github.com/llvm/llvm-project/commit/6595cb1dbb4074d3dcf5dd4a11ec89aee530b135.diff
LOG: [m68k] Implement BSR Instruction
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D143315
Added:
llvm/test/MC/M68k/Control/bsr.s
llvm/test/MC/M68k/Relaxations/bsr.s
Modified:
llvm/lib/Target/M68k/M68kInstrControl.td
llvm/test/MC/Disassembler/M68k/control.txt
llvm/test/MC/M68k/Relocations/text-plt.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kInstrControl.td b/llvm/lib/Target/M68k/M68kInstrControl.td
index 2bdbb824e2f2d..225f932f33166 100644
--- a/llvm/lib/Target/M68k/M68kInstrControl.td
+++ b/llvm/lib/Target/M68k/M68kInstrControl.td
@@ -12,7 +12,7 @@
///
/// Machine:
///
-/// BRA [x] BSR [ ] Bcc [~] DBcc [ ] FBcc [ ]
+/// BRA [x] BSR [~] Bcc [~] DBcc [ ] FBcc [ ]
/// FDBcc [ ] FNOP [ ] FPn [ ] FScc [ ] FTST [ ]
/// JMP [~] JSR [x] NOP [x] RTD [!] RTR [ ]
/// RTS [x] Scc [~] TST [ ]
@@ -225,6 +225,34 @@ def BRA16 : MxBra<MxBrTarget16, (descend 0b0000, 0b0000),
def : Pat<(br bb:$target), (BRA8 MxBrTarget8:$target)>;
+/// -------------------------------------------------
+/// F E D C B A 9 8 | 7 6 5 4 3 2 1 0
+/// -------------------------------------------------
+/// 0 1 1 0 0 0 0 1 | 8-BIT DISPLACEMENT
+/// -------------------------------------------------
+/// 16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
+/// -------------------------------------------------
+/// 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
+/// -------------------------------------------------
+
+let isBranch = 1, isTerminator = 1 in
+class MxBsr<Operand TARGET, MxType TYPE, dag disp_8, dag disp_16_32>
+ : MxInst<(outs), (ins TARGET:$dst), "bsr."#TYPE.Prefix#"\t$dst"> {
+ let Inst = (ascend
+ (descend 0b0110, 0b0001, disp_8),
+ disp_16_32
+ );
+}
+
+def BSR8 : MxBsr<MxBrTarget8, MxType8,
+ (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
+
+def BSR16 : MxBsr<MxBrTarget16, MxType16, (descend 0b0000, 0b0000),
+ (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
+
+def BSR32 : MxBsr<MxBrTarget32, MxType32, (descend 0b1111, 0b1111),
+ (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
+ (decoder "DecodeImm32"))>;
//===----------------------------------------------------------------------===//
// Call
diff --git a/llvm/test/MC/Disassembler/M68k/control.txt b/llvm/test/MC/Disassembler/M68k/control.txt
index 8140e28ac7e6b..d722dfd791fa9 100644
--- a/llvm/test/MC/Disassembler/M68k/control.txt
+++ b/llvm/test/MC/Disassembler/M68k/control.txt
@@ -12,3 +12,12 @@
0x5e 0xc0
# CHECK: nop
0x4e 0x71
+
+# CHECK: bsr.b $1
+0x61 0x01
+
+# CHECK: bsr.w $f01
+0x61 0x00 0x0f 0x01
+
+# CHECK: bsr.l $f0001
+0x61 0xff 0x00 0x0f 0x00 0x01
diff --git a/llvm/test/MC/M68k/Control/bsr.s b/llvm/test/MC/M68k/Control/bsr.s
new file mode 100644
index 0000000000000..a70c7fb9a96ed
--- /dev/null
+++ b/llvm/test/MC/M68k/Control/bsr.s
@@ -0,0 +1,35 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+ ; CHECK: bsr.b .LBB0_1
+ ; CHECK-SAME: encoding: [0x61,A]
+ ; CHECK: fixup A - offset: 1, value: .LBB0_1-1, kind: FK_PCRel_1
+ bsr.b .LBB0_1
+ ; CHECK: bsr.w .LBB0_2
+ ; CHECK-SAME: encoding: [0x61,0x00,A,A]
+ ; CHECK: fixup A - offset: 2, value: .LBB0_2, kind: FK_PCRel_2
+ bsr.w .LBB0_2
+ ; CHECK: bsr.l .LBB0_3
+ ; CHECK-SAME: encoding: [0x61,0xff,A,A,A,A]
+ ; CHECK: fixup A - offset: 2, value: .LBB0_3, kind: FK_PCRel_4
+ bsr.l .LBB0_3
+.LBB0_1:
+ ; CHECK: add.l #0, %d0
+ ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x00]
+ add.l #0, %d0
+ ; CHECK: rts
+ ; CHECK-SAME: encoding: [0x4e,0x75]
+ rts
+.LBB0_2:
+ ; CHECK: add.l #1, %d0
+ ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x01]
+ add.l #1, %d0
+ ; CHECK: rts
+ ; CHECK-SAME: encoding: [0x4e,0x75]
+ rts
+.LBB0_3:
+ ; CHECK: add.l #1, %d0
+ ; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x00,0x00,0x01]
+ add.l #1, %d0
+ ; CHECK: rts
+ ; CHECK-SAME: encoding: [0x4e,0x75]
+ rts
diff --git a/llvm/test/MC/M68k/Relaxations/bsr.s b/llvm/test/MC/M68k/Relaxations/bsr.s
new file mode 100644
index 0000000000000..63021ef5af09c
--- /dev/null
+++ b/llvm/test/MC/M68k/Relaxations/bsr.s
@@ -0,0 +1,51 @@
+; RUN: llvm-mc -triple=m68k -motorola-integers -filetype=obj < %s \
+; RUN: | llvm-objdump -d - | FileCheck %s
+
+; CHECK-LABEL: <TIGHT>:
+TIGHT:
+ ; CHECK: bsr.w $7a
+ bsr.w .LBB0_2
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+.LBB0_2:
+ add.l #0, %d0
+ rts
+
+; CHECK-LABEL: <RELAXED>:
+RELAXED:
+ ; CHECK: bsr.b $82
+ bsr.b .LBB1_2
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+ move.l $0, $0
+.LBB1_2:
+ add.l #0, %d0
+ rts
+
+; CHECK-LABEL: <ZERO>:
+ZERO:
+ ; CHECK: bsr.w $2
+ bsr.w .LBB2_1
+.LBB2_1:
+ add.l #0, %d0
+ rts
diff --git a/llvm/test/MC/M68k/Relocations/text-plt.s b/llvm/test/MC/M68k/Relocations/text-plt.s
index 609908ce7c917..9513519c33c67 100644
--- a/llvm/test/MC/M68k/Relocations/text-plt.s
+++ b/llvm/test/MC/M68k/Relocations/text-plt.s
@@ -7,3 +7,8 @@
; INSTR: jsr (target at PLT,%pc)
; FIXUP: fixup A - offset: 2, value: target at PLT, kind: FK_PCRel_2
jsr (target at PLT,%pc)
+
+; RELOC: R_68K_PLT32 __tls_get_addr 0x0
+; INSTR: bsr.l __tls_get_addr at PLT
+; FIXUP: fixup A - offset: 2, value: __tls_get_addr at PLT, kind: FK_PCRel_4
+bsr.l __tls_get_addr at PLT
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