[PATCH] D143335: [AMDGPU] Use instruction order in machine function to process workList of moveToVALU

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 2 15:23:56 PDT 2023

Previous message: [PATCH] D152039: [RISCV] Remove uses of RISCVII::hasMergeOp from RISCVDAGToDAGISel.cpp
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arsenm requested changes to this revision.
arsenm added a comment.
This revision now requires changes to proceed.

Can this be abandoned now?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143335/new/

https://reviews.llvm.org/D143335

Previous message: [PATCH] D152039: [RISCV] Remove uses of RISCVII::hasMergeOp from RISCVDAGToDAGISel.cpp
Next message: [PATCH] D152041: [profi] Move out base definitions into SampleProfileInferenceBase header
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