[PATCH] D152026: [AMDGPU] WIP: Use implicit operands instead of RegScavenger for AGPR copy lowering on gfx908

[Jeffrey Byrnes via Phabricator via llvm-commits]

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By attaching implicit vgpr to these copies, they will be allocated and available at time of copy lowering, so we no longer need register scavenging. The price is that in high RP kernel, this may cause additional spilling.

This is a WIP while I investigate what is needed to do the same for AGPR copy "spills" (and potentially remove VGPRForAGPRCopy).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152026

Files:
  llvm/include/llvm/CodeGen/LiveRangeEdit.h
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/LiveRangeEdit.cpp
  llvm/lib/CodeGen/MachineInstr.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
  llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
  llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
  llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
  llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
  llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
  llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll

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