[PATCH] D151449: [RISCV] Add DAG combine for CTTZ in the case of input 0

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11445
+  auto ZeroConstant = dyn_cast<ConstantSDNode>(Op2);
+  if (!ZeroConstant || !ZeroConstant->isZero())
+    return SDValue();
----------------
!isNullConstant(Op2)


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11456
+  SDValue Zero = Op1->getOperand(1);
+  if (!isNullConstant(Zero))
+    return SDValue();
----------------
`!isNullConstant(Op1->getOperand(1)`. We don't need the temporary variable `Zero`


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11469
+
+  auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CTTZ.getValueType(), CTTZ,
+                             BitWidthMinusOne);
----------------
If the CTTZ opcode is CTTZ_ZERO_UNDEF, we need to change it to CTTZ.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449