[PATCH] D150899: [PowerPC] Add DFP compare instructions.
Stefan Pintilie via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 2 09:48:47 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG94cefe41e6f2: [PowerPC] Add DFP compare instructions. (authored by stefanp).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150899/new/
https://reviews.llvm.org/D150899
Files:
llvm/lib/Target/PowerPC/PPCInstrDFP.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
Index: llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -50,3 +50,15 @@
# CHECK-BE: ddivq. 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x45]
# CHECK-LE: ddivq. 2, 6, 4 # encoding: [0x45,0x24,0x46,0xfc]
ddivq. 2, 6, 4
+# CHECK-BE: dcmpu 2, 6, 4 # encoding: [0xed,0x06,0x25,0x04]
+# CHECK-LE: dcmpu 2, 6, 4 # encoding: [0x04,0x25,0x06,0xed]
+ dcmpu 2, 6, 4
+# CHECK-BE: dcmpuq 2, 6, 4 # encoding: [0xfd,0x06,0x25,0x04]
+# CHECK-LE: dcmpuq 2, 6, 4 # encoding: [0x04,0x25,0x06,0xfd]
+ dcmpuq 2, 6, 4
+# CHECK-BE: dcmpo 2, 6, 4 # encoding: [0xed,0x06,0x21,0x04]
+# CHECK-LE: dcmpo 2, 6, 4 # encoding: [0x04,0x21,0x06,0xed]
+ dcmpo 2, 6, 4
+# CHECK-BE: dcmpoq 2, 6, 4 # encoding: [0xfd,0x06,0x21,0x04]
+# CHECK-LE: dcmpoq 2, 6, 4 # encoding: [0x04,0x21,0x06,0xfd]
+ dcmpoq 2, 6, 4
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -47,3 +47,15 @@
# CHECK: ddivq. 2, 6, 4
0xfc 0x46 0x24 0x45
+
+# CHECK: dcmpu 2, 6, 4
+0xed 0x06 0x25 0x04
+
+# CHECK: dcmpuq 2, 6, 4
+0xfd 0x06 0x25 0x04
+
+# CHECK: dcmpo 2, 6, 4
+0xed 0x06 0x21 0x04
+
+# CHECK: dcmpoq 2, 6, 4
+0xfd 0x06 0x21 0x04
Index: llvm/lib/Target/PowerPC/PPCInstrDFP.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -13,11 +13,15 @@
// We provide no scheduling info for the DFP instructions.
// While they are not pseudo instructions we don't intend on scheduling them.
let hasNoSchedulingInfo = 1 in {
+let mayRaiseFPException = 1, hasSideEffects = 0 in {
+
+let isCommutable = 1 in {
defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"dadd", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
+}
defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>;
@@ -25,16 +29,33 @@
defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
+let isCommutable = 1 in {
defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"dmul", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"dmulq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
+}
defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"ddiv", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"ddivq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+let isCompare = 1 in {
+ def DCMPU : XForm_17<59, 642, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+ "dcmpu $BF, $RA, $RB", IIC_FPCompare>;
+
+ def DCMPUQ : XForm_17<63, 642, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
+ "dcmpuq $BF, $RA, $RB", IIC_FPCompare>;
+
+ def DCMPO : XForm_17<59, 130, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+ "dcmpo $BF, $RA, $RB", IIC_FPCompare>;
+
+ def DCMPOQ : XForm_17<63, 130, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
+ "dcmpoq $BF, $RA, $RB", IIC_FPCompare>;
+}
+}
}
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