[llvm] a854f06 - [AArch64] Add SVE predicated operations tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 2 07:08:10 PDT 2023
Author: David Green
Date: 2023-06-02T15:08:04+01:00
New Revision: a854f06e0fe97adefec0957ab0118388fe5a11af
URL: https://github.com/llvm/llvm-project/commit/a854f06e0fe97adefec0957ab0118388fe5a11af
DIFF: https://github.com/llvm/llvm-project/commit/a854f06e0fe97adefec0957ab0118388fe5a11af.diff
LOG: [AArch64] Add SVE predicated operations tests. NFC
Originally from the MVE tests, this adds tests for various operations which can
often be converted to predicated instructions under SVE. Additionally some tests
for commutativity and extra uses of the existing smin/smax operations. See the
patches D149969/ D151084 / D151080 / D149967 / etc.
Added:
llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
Modified:
llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll b/llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
index 2d4d0b74a08e1..1d046f007cca2 100644
--- a/llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
@@ -5,10 +5,10 @@ define i64 @scalable_int_min_max(ptr %arg, ptr %arg1, <vscale x 2 x ptr> %i37, <
; CHECK-LABEL: scalable_int_min_max:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #3745
+; CHECK-NEXT: mov w8, #3745 // =0xea1
; CHECK-NEXT: movk w8, #16618, lsl #16
; CHECK-NEXT: ld1w { z3.d }, p0/z, [x0]
-; CHECK-NEXT: mov w9, #57344
+; CHECK-NEXT: mov w9, #57344 // =0xe000
; CHECK-NEXT: mov z6.d, #1023 // =0x3ff
; CHECK-NEXT: movk w9, #17535, lsl #16
; CHECK-NEXT: mov z4.s, w8
diff --git a/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll b/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
index 9fbbb8e4a433d..8558620080be5 100644
--- a/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
+++ b/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
@@ -173,6 +173,70 @@ define <vscale x 2 x i64> @umin_select_i64(<vscale x 2 x i1> %pg, <vscale x 2 x
}
+define <vscale x 2 x i64> @umin_select_i64_multiuse(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
+; CHECK-LABEL: umin_select_i64_multiuse:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: umin z2.d, p1/m, z2.d, z1.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: st1d { z2.d }, p1, [x0]
+; CHECK-NEXT: ret
+ %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ store <vscale x 2 x i64> %sel, ptr %p
+ %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @smin_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: smin_select_i64_c:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: smin z0.d, p1/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = call <vscale x 2 x i64> @llvm.smin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @smax_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: smax_select_i64_c:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: smax z0.d, p1/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = call <vscale x 2 x i64> @llvm.smax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @umin_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: umin_select_i64_c:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: umin z0.d, p1/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %out
+}
+
+define <vscale x 2 x i64> @umax_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: umax_select_i64_c:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: umax z0.d, p1/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b
+ ret <vscale x 2 x i64> %out
+}
+
+
declare <vscale x 16 x i8> @llvm.smax.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.smax.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
new file mode 100644
index 0000000000000..f7cc43c3c2b31
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
@@ -0,0 +1,1405 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+neon,+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+
+define <vscale x 4 x i32> @add_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: add_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: add z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = add <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @add_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: add_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: add z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = add <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @add_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: add_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: add z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = add <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @sub_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: sub_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sub z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = sub <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sub_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: sub_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sub z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = sub <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sub_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: sub_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sub z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = sub <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @mul_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: mul_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mul z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = mul <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mul_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: mul_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mul z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = mul <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mul_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: mul_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mul z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = mul <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @and_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: and_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: and z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = and <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @and_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: and_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: and z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = and <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @and_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: and_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: and z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = and <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @or_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: or_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = or <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @or_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: or_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = or <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @or_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: or_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = or <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @xor_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: xor_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: eor z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = xor <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @xor_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: xor_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: eor z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = xor <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @xor_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: xor_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: eor z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = xor <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @andnot_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: andnot_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: bic z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %y1 = xor <vscale x 4 x i32> %y, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %a = and <vscale x 4 x i32> %x, %y1
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @andnot_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: andnot_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: bic z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %y1 = xor <vscale x 8 x i16> %y, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %a = and <vscale x 8 x i16> %x, %y1
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @andnot_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: andnot_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: bic z1.d, z1.d, z2.d
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %y1 = xor <vscale x 16 x i8> %y, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i32 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %a = and <vscale x 16 x i8> %x, %y1
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @ornot_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: ornot_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z3.s, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: eor z2.d, z2.d, z3.d
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %y1 = xor <vscale x 4 x i32> %y, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %a = or <vscale x 4 x i32> %x, %y1
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ornot_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: ornot_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z3.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: eor z2.d, z2.d, z3.d
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %y1 = xor <vscale x 8 x i16> %y, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %a = or <vscale x 8 x i16> %x, %y1
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ornot_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: ornot_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z3.b, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: eor z2.d, z2.d, z3.d
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: orr z1.d, z1.d, z2.d
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %y1 = xor <vscale x 16 x i8> %y, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i32 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %a = or <vscale x 16 x i8> %x, %y1
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fadd_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {
+; CHECK-LABEL: fadd_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fadd z1.s, z1.s, z2.s
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %a = fadd <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fadd_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {
+; CHECK-LABEL: fadd_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fadd z1.h, z1.h, z2.h
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %a = fadd <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x float> @fsub_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {
+; CHECK-LABEL: fsub_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsub z1.s, z1.s, z2.s
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %a = fsub <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsub_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {
+; CHECK-LABEL: fsub_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fsub z1.h, z1.h, z2.h
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %a = fsub <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x float> @fmul_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {
+; CHECK-LABEL: fmul_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmul z1.s, z1.s, z2.s
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %a = fmul <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmul_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {
+; CHECK-LABEL: fmul_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmul z1.h, z1.h, z2.h
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %a = fmul <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x i32> @icmp_slt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: icmp_slt_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: smin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a1 = icmp slt <vscale x 4 x i32> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @icmp_slt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: icmp_slt_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: smin z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a1 = icmp slt <vscale x 8 x i16> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @icmp_slt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: icmp_slt_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: smin z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a1 = icmp slt <vscale x 16 x i8> %x, %y
+ %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @icmp_sgt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: icmp_sgt_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: smax z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a1 = icmp sgt <vscale x 4 x i32> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @icmp_sgt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: icmp_sgt_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: smax z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a1 = icmp sgt <vscale x 8 x i16> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @icmp_sgt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: icmp_sgt_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: smax z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a1 = icmp sgt <vscale x 16 x i8> %x, %y
+ %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @icmp_ult_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: icmp_ult_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: umin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a1 = icmp ult <vscale x 4 x i32> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @icmp_ult_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: icmp_ult_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: umin z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a1 = icmp ult <vscale x 8 x i16> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @icmp_ult_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: icmp_ult_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: umin z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a1 = icmp ult <vscale x 16 x i8> %x, %y
+ %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @icmp_ugt_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: icmp_ugt_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: umax z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a1 = icmp ugt <vscale x 4 x i32> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @icmp_ugt_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: icmp_ugt_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: umax z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a1 = icmp ugt <vscale x 8 x i16> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @icmp_ugt_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: icmp_ugt_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: umax z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a1 = icmp ugt <vscale x 16 x i8> %x, %y
+ %a = select <vscale x 16 x i1> %a1, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fcmp_fast_olt_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {
+; CHECK-LABEL: fcmp_fast_olt_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %a1 = fcmp fast olt <vscale x 4 x float> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x float> %x, <vscale x 4 x float> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fcmp_fast_olt_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {
+; CHECK-LABEL: fcmp_fast_olt_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fminnm z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %a1 = fcmp fast olt <vscale x 8 x half> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x half> %x, <vscale x 8 x half> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x float> @fcmp_fast_ogt_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, <vscale x 4 x float> %y) {
+; CHECK-LABEL: fcmp_fast_ogt_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %a1 = fcmp fast ogt <vscale x 4 x float> %x, %y
+ %a = select <vscale x 4 x i1> %a1, <vscale x 4 x float> %x, <vscale x 4 x float> %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fcmp_fast_ogt_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, <vscale x 8 x half> %y) {
+; CHECK-LABEL: fcmp_fast_ogt_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmaxnm z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %a1 = fcmp fast ogt <vscale x 8 x half> %x, %y
+ %a = select <vscale x 8 x i1> %a1, <vscale x 8 x half> %x, <vscale x 8 x half> %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x i32> @sadd_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: sadd_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sqadd z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sadd_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: sadd_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sqadd z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sadd_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: sadd_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sqadd z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @uadd_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: uadd_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uqadd z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @uadd_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: uadd_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uqadd z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @uadd_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: uadd_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uqadd z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @ssub_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: ssub_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sqsub z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ssub_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: ssub_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sqsub z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ssub_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: ssub_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sqsub z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @usub_sat_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: usub_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uqsub z1.s, z1.s, z2.s
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @usub_sat_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
+; CHECK-LABEL: usub_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uqsub z1.h, z1.h, z2.h
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @usub_sat_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
+; CHECK-LABEL: usub_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uqsub z1.b, z1.b, z2.b
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @addqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: addqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: add z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = add <vscale x 4 x i32> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @addqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: addqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: add z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = add <vscale x 8 x i16> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @addqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: addqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: add z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = add <vscale x 16 x i8> %x, %ys
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @subqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: subqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: sub z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = sub <vscale x 4 x i32> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @subqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: subqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: sub z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = sub <vscale x 8 x i16> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @subqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: subqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: sub z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = sub <vscale x 16 x i8> %x, %ys
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @mulqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: mulqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: mul z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = mul <vscale x 4 x i32> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mulqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: mulqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: mul z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = mul <vscale x 8 x i16> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mulqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: mulqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: mul z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = mul <vscale x 16 x i8> %x, %ys
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @faddqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {
+; CHECK-LABEL: faddqr_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $z2
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, s2
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: fadd z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x float> undef, float %y, i32 0
+ %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+ %a = fadd <vscale x 4 x float> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @faddqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {
+; CHECK-LABEL: faddqr_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h2 killed $h2 def $z2
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, h2
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: fadd z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x half> undef, half %y, i32 0
+ %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+ %a = fadd <vscale x 8 x half> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x float> @fsubqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {
+; CHECK-LABEL: fsubqr_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $z2
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, s2
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: fsub z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x float> undef, float %y, i32 0
+ %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+ %a = fsub <vscale x 4 x float> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsubqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {
+; CHECK-LABEL: fsubqr_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h2 killed $h2 def $z2
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, h2
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: fsub z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x half> undef, half %y, i32 0
+ %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+ %a = fsub <vscale x 8 x half> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x float> @fmulqr_v4f32(<vscale x 4 x float> %z, <vscale x 4 x float> %x, float %y) {
+; CHECK-LABEL: fmulqr_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $z2
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, s2
+; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #0.0
+; CHECK-NEXT: fmul z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 4 x float> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x float> undef, float %y, i32 0
+ %ys = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+ %a = fmul <vscale x 4 x float> %x, %ys
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %z
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmulqr_v8f16(<vscale x 8 x half> %z, <vscale x 8 x half> %x, half %y) {
+; CHECK-LABEL: fmulqr_v8f16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h2 killed $h2 def $z2
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, h2
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
+; CHECK-NEXT: fmul z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp oeq <vscale x 8 x half> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x half> undef, half %y, i32 0
+ %ys = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+ %a = fmul <vscale x 8 x half> %x, %ys
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %z
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 4 x i32> @sadd_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: sadd_satqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: sqadd z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sadd_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: sadd_satqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: sqadd z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sadd_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: sadd_satqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: sqadd z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @uadd_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: uadd_satqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: uqadd z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @uadd_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: uadd_satqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: uqadd z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @uadd_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: uadd_satqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: uqadd z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @ssub_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: ssub_satqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: sqsub z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ssub_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: ssub_satqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: sqsub z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ssub_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: ssub_satqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: sqsub z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x i32> @usub_satqr_v4i32(<vscale x 4 x i32> %z, <vscale x 4 x i32> %x, i32 %y) {
+; CHECK-LABEL: usub_satqr_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mov z2.s, w0
+; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #0
+; CHECK-NEXT: uqsub z1.s, z1.s, z2.s
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 4 x i32> %z, zeroinitializer
+ %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
+ %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %a = call <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %ys)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %z
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @usub_satqr_v8i16(<vscale x 8 x i16> %z, <vscale x 8 x i16> %x, i16 %y) {
+; CHECK-LABEL: usub_satqr_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mov z2.h, w0
+; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #0
+; CHECK-NEXT: uqsub z1.h, z1.h, z2.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 8 x i16> %z, zeroinitializer
+ %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
+ %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %a = call <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %ys)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %z
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @usub_satqr_v16i8(<vscale x 16 x i8> %z, <vscale x 16 x i8> %x, i8 %y) {
+; CHECK-LABEL: usub_satqr_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mov z2.b, w0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
+; CHECK-NEXT: uqsub z1.b, z1.b, z2.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp eq <vscale x 16 x i8> %z, zeroinitializer
+ %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
+ %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %a = call <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %ys)
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %z
+ ret <vscale x 16 x i8> %b
+}
+
+declare <vscale x 16 x i8> @llvm.sadd.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)
+declare <vscale x 8 x i16> @llvm.sadd.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)
+declare <vscale x 4 x i32> @llvm.sadd.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)
+declare <vscale x 16 x i8> @llvm.uadd.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)
+declare <vscale x 8 x i16> @llvm.uadd.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)
+declare <vscale x 4 x i32> @llvm.uadd.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)
+declare <vscale x 16 x i8> @llvm.ssub.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)
+declare <vscale x 8 x i16> @llvm.ssub.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)
+declare <vscale x 4 x i32> @llvm.ssub.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)
+declare <vscale x 16 x i8> @llvm.usub.sat.v16i8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2)
+declare <vscale x 8 x i16> @llvm.usub.sat.v8i16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2)
+declare <vscale x 4 x i32> @llvm.usub.sat.v4i32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2)
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
new file mode 100644
index 0000000000000..21a2c14cc8bc1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
@@ -0,0 +1,2647 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+
+define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: add_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: add z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = add <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: add_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: add z1.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = add <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @add_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: add_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: add z1.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = add <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @add_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: add_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: add z1.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = add <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sub_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sub_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: sub z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = sub <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sub_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sub_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sub z1.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = sub <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sub_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sub_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sub z1.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = sub <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sub_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sub_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sub z1.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = sub <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mul_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mul_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mul z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = mul <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mul_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mul_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mul z1.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = mul <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mul_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mul_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mul z1.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = mul <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mul_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mul_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mul z1.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = mul <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sdiv_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sdiv_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: sdivr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = sdiv <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sdiv_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sdiv_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = sdiv <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sdiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sdiv_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: sunpkhi z3.s, z1.h
+; CHECK-NEXT: sunpkhi z4.s, z0.h
+; CHECK-NEXT: sunpklo z1.s, z1.h
+; CHECK-NEXT: sunpklo z5.s, z0.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sdivr z3.s, p1/m, z3.s, z4.s
+; CHECK-NEXT: sdivr z1.s, p1/m, z1.s, z5.s
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = sdiv <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sdiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sdiv_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sunpkhi z3.h, z1.b
+; CHECK-NEXT: sunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z5.s, z3.h
+; CHECK-NEXT: sunpkhi z6.s, z4.h
+; CHECK-NEXT: sunpklo z1.h, z1.b
+; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: sunpklo z6.h, z0.b
+; CHECK-NEXT: sunpklo z3.s, z3.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sunpkhi z7.s, z1.h
+; CHECK-NEXT: sunpkhi z24.s, z6.h
+; CHECK-NEXT: sunpklo z1.s, z1.h
+; CHECK-NEXT: sunpklo z6.s, z6.h
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z6.s
+; CHECK-NEXT: movprfx z4, z24
+; CHECK-NEXT: sdiv z4.s, p0/m, z4.s, z7.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z1.h, z1.h, z4.h
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = sdiv <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @udiv_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: udiv_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: udivr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = udiv <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @udiv_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: udiv_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = udiv <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @udiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: udiv_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: uunpkhi z3.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z5.s, z0.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: udivr z3.s, p1/m, z3.s, z4.s
+; CHECK-NEXT: udivr z1.s, p1/m, z1.s, z5.s
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = udiv <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @udiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: udiv_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uunpkhi z3.h, z1.b
+; CHECK-NEXT: uunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z5.s, z3.h
+; CHECK-NEXT: uunpkhi z6.s, z4.h
+; CHECK-NEXT: uunpklo z1.h, z1.b
+; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: uunpklo z6.h, z0.b
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: uunpkhi z7.s, z1.h
+; CHECK-NEXT: uunpkhi z24.s, z6.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z6.s, z6.h
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z6.s
+; CHECK-NEXT: movprfx z4, z24
+; CHECK-NEXT: udiv z4.s, p0/m, z4.s, z7.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z1.h, z1.h, z4.h
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = udiv <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @srem_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: srem_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: sdiv z2.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: msb z1.d, p0/m, z2.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = srem <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @srem_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: srem_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: msb z1.s, p0/m, z2.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = srem <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @srem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: srem_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z3.s, z1.h
+; CHECK-NEXT: sunpkhi z4.s, z0.h
+; CHECK-NEXT: sunpklo z5.s, z1.h
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: sunpklo z6.s, z0.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: sdiv z4.s, p0/m, z4.s, z5.s
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: msb z1.h, p0/m, z3.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = srem <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @srem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: srem_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sunpkhi z3.h, z1.b
+; CHECK-NEXT: sunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z5.s, z3.h
+; CHECK-NEXT: sunpkhi z6.s, z4.h
+; CHECK-NEXT: sunpklo z3.s, z3.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: sunpklo z4.h, z1.b
+; CHECK-NEXT: sunpklo z6.h, z0.b
+; CHECK-NEXT: sunpkhi z7.s, z4.h
+; CHECK-NEXT: sunpkhi z24.s, z6.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sunpklo z6.s, z6.h
+; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s
+; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.b, z4.b, z3.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: msb z1.b, p0/m, z3.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = srem <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @urem_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: urem_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: msb z1.d, p0/m, z2.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = urem <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @urem_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: urem_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: msb z1.s, p0/m, z2.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = urem <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @urem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: urem_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z3.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z0.h
+; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: uunpklo z6.s, z0.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: udiv z4.s, p0/m, z4.s, z5.s
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: msb z1.h, p0/m, z3.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = urem <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @urem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: urem_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uunpkhi z3.h, z1.b
+; CHECK-NEXT: uunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z5.s, z3.h
+; CHECK-NEXT: uunpkhi z6.s, z4.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: uunpklo z4.h, z1.b
+; CHECK-NEXT: uunpklo z6.h, z0.b
+; CHECK-NEXT: uunpkhi z7.s, z4.h
+; CHECK-NEXT: uunpkhi z24.s, z6.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: uunpklo z6.s, z6.h
+; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s
+; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.b, z4.b, z3.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: msb z1.b, p0/m, z3.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = urem <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @and_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: and_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: and z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = and <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @and_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: and_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: and z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = and <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @and_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: and_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: and z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = and <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @and_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: and_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: and z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = and <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @or_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: or_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: orr z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = or <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @or_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: or_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: orr z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = or <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @or_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: or_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: orr z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = or <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @or_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: or_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: orr z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = or <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @xor_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: xor_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: eor z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = xor <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @xor_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: xor_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: eor z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = xor <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @xor_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: xor_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: eor z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = xor <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @xor_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: xor_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: eor z1.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = xor <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @shl_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: shl_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lslr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = shl <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @shl_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: shl_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = shl <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @shl_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: shl_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lslr z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = shl <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @shl_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: shl_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lslr z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = shl <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @ashr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: ashr_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: asrr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = ashr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @ashr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: ashr_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: asrr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = ashr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ashr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: ashr_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: asrr z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = ashr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ashr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: ashr_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: asrr z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = ashr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @lshr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: lshr_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lsrr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = lshr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @lshr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: lshr_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lsrr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = lshr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @lshr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: lshr_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lsrr z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = lshr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @lshr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: lshr_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lsrr z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = lshr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mla_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mla_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: mad z1.d, p0/m, z2.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %y, %z
+ %a = add <vscale x 2 x i64> %x, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mla_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mla_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: mad z1.s, p0/m, z2.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %y, %z
+ %a = add <vscale x 4 x i32> %x, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mla_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mla_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: mad z1.h, p0/m, z2.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %y, %z
+ %a = add <vscale x 8 x i16> %x, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mla_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mla_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: mad z1.b, p0/m, z2.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %y, %z
+ %a = add <vscale x 16 x i8> %x, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mls_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mls_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: msb z1.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %x, %y
+ %a = sub <vscale x 2 x i64> %z, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mls_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mls_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: msb z1.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %x, %y
+ %a = sub <vscale x 4 x i32> %z, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mls_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mls_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: msb z1.h, p0/m, z0.h, z2.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %x, %y
+ %a = sub <vscale x 8 x i16> %z, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mls_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mls_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: msb z1.b, p0/m, z0.b, z2.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %x, %y
+ %a = sub <vscale x 16 x i8> %z, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fadd_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fadd_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fadd <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fadd_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fadd_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fadd <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fadd_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fadd_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fadd <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fsub_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fsub_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fsub <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsub_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fsub_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fsub <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fsub_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fsub_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fsub <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmul_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmul_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fmul <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmul_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmul_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fmul <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmul_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmul_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fmul <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fdiv_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fdiv_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fdivr z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fdiv <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fdiv_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fdiv_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fdivr z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fdiv <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fdiv_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fdiv_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fdivr z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fdiv <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmai_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmai_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmai_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmai_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmai_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmai_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fma_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fma_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %m = fmul fast <vscale x 4 x float> %y, %z
+ %a = fadd fast <vscale x 4 x float> %m, %x
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fma_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fma_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %m = fmul fast <vscale x 8 x half> %y, %z
+ %a = fadd fast <vscale x 8 x half> %m, %x
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fma_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fma_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %m = fmul fast <vscale x 2 x double> %y, %z
+ %a = fadd fast <vscale x 2 x double> %m, %x
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 2 x i64> @add_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: add_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: add z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = add <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: add_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = add <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @add_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: add_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: add z0.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = add <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @add_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: add_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: add z0.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = add <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sub_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sub_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: sub z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = sub <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sub_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sub_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sub z0.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = sub <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sub_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sub_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sub z0.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = sub <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sub_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sub_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sub z0.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = sub <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mul_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mul_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: mul z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = mul <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mul_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mul_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mul z0.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = mul <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mul_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mul_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: mul z0.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = mul <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mul_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mul_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: mul z0.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = mul <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sdiv_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sdiv_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = sdiv <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sdiv_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sdiv_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = sdiv <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sdiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sdiv_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: sunpkhi z3.s, z1.h
+; CHECK-NEXT: sunpkhi z4.s, z0.h
+; CHECK-NEXT: sunpklo z5.s, z1.h
+; CHECK-NEXT: sunpklo z0.s, z0.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sdivr z3.s, p1/m, z3.s, z4.s
+; CHECK-NEXT: sdiv z0.s, p1/m, z0.s, z5.s
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = sdiv <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sdiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sdiv_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sunpkhi z3.h, z1.b
+; CHECK-NEXT: sunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z5.s, z3.h
+; CHECK-NEXT: sunpkhi z6.s, z4.h
+; CHECK-NEXT: sunpklo z7.h, z1.b
+; CHECK-NEXT: sunpklo z3.s, z3.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: sunpklo z0.h, z0.b
+; CHECK-NEXT: sunpkhi z6.s, z7.h
+; CHECK-NEXT: sunpkhi z24.s, z0.h
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: movprfx z4, z24
+; CHECK-NEXT: sdiv z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: sunpklo z6.s, z7.h
+; CHECK-NEXT: sunpklo z0.s, z0.h
+; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z6.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z0.h, z0.h, z4.h
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = sdiv <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @udiv_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: udiv_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = udiv <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @udiv_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: udiv_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = udiv <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @udiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: udiv_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: uunpkhi z3.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z0.h
+; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: udivr z3.s, p1/m, z3.s, z4.s
+; CHECK-NEXT: udiv z0.s, p1/m, z0.s, z5.s
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = udiv <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @udiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: udiv_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uunpkhi z3.h, z1.b
+; CHECK-NEXT: uunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z5.s, z3.h
+; CHECK-NEXT: uunpkhi z6.s, z4.h
+; CHECK-NEXT: uunpklo z7.h, z1.b
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: uunpklo z0.h, z0.b
+; CHECK-NEXT: uunpkhi z6.s, z7.h
+; CHECK-NEXT: uunpkhi z24.s, z0.h
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: movprfx z4, z24
+; CHECK-NEXT: udiv z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: uunpklo z6.s, z7.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z6.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z0.h, z0.h, z4.h
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = udiv <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @srem_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: srem_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: sdiv z2.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = srem <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @srem_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: srem_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = srem <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @srem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: srem_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z3.s, z1.h
+; CHECK-NEXT: sunpkhi z4.s, z0.h
+; CHECK-NEXT: sunpklo z5.s, z1.h
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: sunpklo z6.s, z0.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: sdiv z4.s, p0/m, z4.s, z5.s
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: mls z0.h, p0/m, z3.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = srem <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @srem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: srem_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sunpkhi z3.h, z1.b
+; CHECK-NEXT: sunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sunpkhi z5.s, z3.h
+; CHECK-NEXT: sunpkhi z6.s, z4.h
+; CHECK-NEXT: sunpklo z3.s, z3.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: sunpklo z4.h, z1.b
+; CHECK-NEXT: sunpklo z6.h, z0.b
+; CHECK-NEXT: sunpkhi z7.s, z4.h
+; CHECK-NEXT: sunpkhi z24.s, z6.h
+; CHECK-NEXT: sunpklo z4.s, z4.h
+; CHECK-NEXT: sunpklo z6.s, z6.h
+; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s
+; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.b, z4.b, z3.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: mls z0.b, p0/m, z3.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = srem <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @urem_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: urem_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = urem <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @urem_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: urem_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = urem <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @urem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: urem_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z3.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z0.h
+; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: uunpklo z6.s, z0.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: udiv z4.s, p0/m, z4.s, z5.s
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: mls z0.h, p0/m, z3.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = urem <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @urem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: urem_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uunpkhi z3.h, z1.b
+; CHECK-NEXT: uunpkhi z4.h, z0.b
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uunpkhi z5.s, z3.h
+; CHECK-NEXT: uunpkhi z6.s, z4.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s
+; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
+; CHECK-NEXT: uunpklo z4.h, z1.b
+; CHECK-NEXT: uunpklo z6.h, z0.b
+; CHECK-NEXT: uunpkhi z7.s, z4.h
+; CHECK-NEXT: uunpkhi z24.s, z6.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: uunpklo z6.s, z6.h
+; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s
+; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s
+; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
+; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: uzp1 z3.b, z4.b, z3.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: mls z0.b, p0/m, z3.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = urem <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @and_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: and_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = and <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @and_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: and_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = and <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @and_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: and_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = and <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @and_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: and_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = and <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @or_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: or_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = or <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @or_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: or_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = or <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @or_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: or_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = or <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @or_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: or_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = or <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @xor_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: xor_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = xor <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @xor_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: xor_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = xor <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @xor_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: xor_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = xor <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @xor_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: xor_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = xor <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @shl_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: shl_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = shl <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @shl_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: shl_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = shl <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @shl_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: shl_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = shl <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @shl_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: shl_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = shl <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @ashr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: ashr_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = ashr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @ashr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: ashr_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = ashr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ashr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: ashr_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = ashr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ashr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: ashr_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = ashr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @lshr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: lshr_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = lshr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @lshr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: lshr_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = lshr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @lshr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: lshr_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = lshr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @lshr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: lshr_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = lshr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mla_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mla_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %y, %z
+ %a = add <vscale x 2 x i64> %x, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mla_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mla_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %y, %z
+ %a = add <vscale x 4 x i32> %x, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mla_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mla_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %y, %z
+ %a = add <vscale x 8 x i16> %x, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mla_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mla_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %y, %z
+ %a = add <vscale x 16 x i8> %x, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mls_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mls_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: msb z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %x, %y
+ %a = sub <vscale x 2 x i64> %z, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mls_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mls_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: msb z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %x, %y
+ %a = sub <vscale x 4 x i32> %z, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mls_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mls_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: msb z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %x, %y
+ %a = sub <vscale x 8 x i16> %z, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mls_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mls_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: msb z0.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %x, %y
+ %a = sub <vscale x 16 x i8> %z, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fadd_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fadd_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fadd z0.s, z0.s, z1.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fadd <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fadd_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fadd_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fadd z0.h, z0.h, z1.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fadd <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fadd_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fadd_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fadd z0.d, z0.d, z1.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fadd <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fsub_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fsub_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsub z0.s, z0.s, z1.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fsub <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsub_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fsub_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fsub z0.h, z0.h, z1.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fsub <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fsub_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fsub_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsub z0.d, z0.d, z1.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fsub <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmul_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmul_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmul z0.s, z0.s, z1.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fmul <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmul_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmul_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmul z0.h, z0.h, z1.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fmul <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmul_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmul_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmul z0.d, z0.d, z1.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fmul <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fdiv_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fdiv_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fdiv <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fdiv_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fdiv_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fdiv <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fdiv_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fdiv_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fdiv <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmai_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmai_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmai_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmai_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmai_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmai_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fma_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fma_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %m = fmul fast <vscale x 4 x float> %y, %z
+ %a = fadd fast <vscale x 4 x float> %m, %x
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fma_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fma_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %m = fmul fast <vscale x 8 x half> %y, %z
+ %a = fadd fast <vscale x 8 x half> %m, %x
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fma_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fma_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %m = fmul fast <vscale x 2 x double> %y, %z
+ %a = fadd fast <vscale x 2 x double> %m, %x
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+
+define <vscale x 4 x i32> @mul_use_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n, ptr %p) {
+; CHECK-LABEL: mul_use_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: mul z1.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: st1w { z1.s }, p0, [x0]
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = mul <vscale x 4 x i32> %x, %y
+ store <vscale x 4 x i32> %a, ptr %p
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
new file mode 100644
index 0000000000000..24a6c81a99ad8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
@@ -0,0 +1,1954 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+
+define <vscale x 2 x i64> @add_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: add_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = add <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: add_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = add <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @add_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: add_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = add <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @add_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: add_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = add <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sub_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sub_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = sub <vscale x 2 x i64> %x, %a
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sub_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sub_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = sub <vscale x 4 x i32> %x, %a
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sub_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sub_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = sub <vscale x 8 x i16> %x, %a
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sub_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sub_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = sub <vscale x 16 x i8> %x, %a
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mul_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mul_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #1 // =0x1
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: mul z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = mul <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mul_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mul_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #1 // =0x1
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: mul z0.s, z1.s, z0.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = mul <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mul_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mul_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #1 // =0x1
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: mul z0.h, z1.h, z0.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = mul <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mul_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mul_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #1 // =0x1
+; CHECK-NEXT: sel z1.b, p0, z1.b, z2.b
+; CHECK-NEXT: mul z0.b, z1.b, z0.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %b = mul <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @and_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: and_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: and z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = and <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @and_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: and_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: and z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = and <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @and_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: and_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: and z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = and <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @and_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: and_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z1.b, p0, z1.b, z2.b
+; CHECK-NEXT: and z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %b = and <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @or_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: or_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: orr z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = or <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @or_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: or_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: orr z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = or <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @or_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: or_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: orr z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = or <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @or_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: or_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z1.b, p0, z1.b, z2.b
+; CHECK-NEXT: orr z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = or <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @xor_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: xor_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: eor z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = xor <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @xor_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: xor_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: eor z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = xor <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @xor_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: xor_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: eor z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = xor <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @xor_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: xor_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z1.b, p0, z1.b, z2.b
+; CHECK-NEXT: eor z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = xor <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @shl_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: shl_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z1.d, p1, z1.d, z2.d
+; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = shl <vscale x 2 x i64> %x, %a
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @shl_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: shl_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z1.s, p1, z1.s, z2.s
+; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = shl <vscale x 4 x i32> %x, %a
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @shl_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: shl_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z1.h, p1, z1.h, z2.h
+; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = shl <vscale x 8 x i16> %x, %a
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @shl_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: shl_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z1.b, p1, z1.b, z2.b
+; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = shl <vscale x 16 x i8> %x, %a
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @ashr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: ashr_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z1.d, p1, z1.d, z2.d
+; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = ashr <vscale x 2 x i64> %x, %a
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @ashr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: ashr_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z1.s, p1, z1.s, z2.s
+; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = ashr <vscale x 4 x i32> %x, %a
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ashr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: ashr_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z1.h, p1, z1.h, z2.h
+; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = ashr <vscale x 8 x i16> %x, %a
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ashr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: ashr_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z1.b, p1, z1.b, z2.b
+; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = ashr <vscale x 16 x i8> %x, %a
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @lshr_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: lshr_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z1.d, p1, z1.d, z2.d
+; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %y, <vscale x 2 x i64> zeroinitializer
+ %b = lshr <vscale x 2 x i64> %x, %a
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @lshr_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: lshr_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z1.s, p1, z1.s, z2.s
+; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> zeroinitializer
+ %b = lshr <vscale x 4 x i32> %x, %a
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @lshr_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: lshr_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z1.h, p1, z1.h, z2.h
+; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %y, <vscale x 8 x i16> zeroinitializer
+ %b = lshr <vscale x 8 x i16> %x, %a
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @lshr_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: lshr_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z1.b, p1, z1.b, z2.b
+; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %y, <vscale x 16 x i8> zeroinitializer
+ %b = lshr <vscale x 16 x i8> %x, %a
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mla_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mla_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, #0
+; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %y, %z
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %m, <vscale x 2 x i64> zeroinitializer
+ %b = add <vscale x 2 x i64> %a, %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mla_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mla_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, #0
+; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %y, %z
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %m, <vscale x 4 x i32> zeroinitializer
+ %b = add <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mla_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mla_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, #0
+; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %y, %z
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %m, <vscale x 8 x i16> zeroinitializer
+ %b = add <vscale x 8 x i16> %a, %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mla_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mla_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z3.b, #0
+; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %y, %z
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %m, <vscale x 16 x i8> zeroinitializer
+ %b = add <vscale x 16 x i8> %a, %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mls_nxv2i64_x(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mls_nxv2i64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: msb z1.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: mov z0.d, p1/m, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %x, %y
+ %a = sub <vscale x 2 x i64> %z, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %x
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mls_nxv4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mls_nxv4i32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: msb z1.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: mov z0.s, p1/m, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %x, %y
+ %a = sub <vscale x 4 x i32> %z, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mls_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mls_nxv8i16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: msb z1.h, p0/m, z0.h, z2.h
+; CHECK-NEXT: mov z0.h, p1/m, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %x, %y
+ %a = sub <vscale x 8 x i16> %z, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mls_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mls_nxv16i8_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: msb z1.b, p0/m, z0.b, z2.b
+; CHECK-NEXT: mov z0.b, p1/m, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %x, %y
+ %a = sub <vscale x 16 x i8> %z, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fadd_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fadd_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.s, w8
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: fadd z0.s, z1.s, z0.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float -0.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fadd <vscale x 4 x float> %a, %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fadd_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fadd_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #32768 // =0x8000
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.h, w8
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: fadd z0.h, z1.h, z0.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH8000, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fadd <vscale x 8 x half> %a, %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fadd_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fadd_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.d, x8
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: fadd z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double -0.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fadd <vscale x 2 x double> %a, %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fsub_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fsub_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> zeroinitializer
+ %b = fsub <vscale x 4 x float> %x, %a
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsub_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fsub_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> zeroinitializer
+ %b = fsub <vscale x 8 x half> %x, %a
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fsub_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fsub_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> zeroinitializer
+ %b = fsub <vscale x 2 x double> %x, %a
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmul_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmul_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fmov z2.s, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: fmul z0.s, z1.s, z0.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 1.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fmul <vscale x 4 x float> %a, %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmul_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmul_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fmov z2.h, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: fmul z0.h, z1.h, z0.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH3C00, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fmul <vscale x 8 x half> %a, %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmul_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmul_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fmov z2.d, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: fmul z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 1.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fmul <vscale x 2 x double> %a, %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fdiv_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fdiv_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fmov z2.s, #1.00000000
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.s, p1, z1.s, z2.s
+; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %y, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 1.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fdiv <vscale x 4 x float> %x, %a
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fdiv_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fdiv_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fmov z2.h, #1.00000000
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.h, p1, z1.h, z2.h
+; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %y, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH3C00, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fdiv <vscale x 8 x half> %x, %a
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fdiv_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fdiv_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fmov z2.d, #1.00000000
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z1.d, p1, z1.d, z2.d
+; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %y, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 1.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fdiv <vscale x 2 x double> %x, %a
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fma_nxv4f32_x(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fma_nxv4f32_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: fmul z1.s, z1.s, z2.s
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.s, w8
+; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
+; CHECK-NEXT: fadd z0.s, z1.s, z0.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %m = fmul fast <vscale x 4 x float> %y, %z
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %m, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float -0.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fadd fast <vscale x 4 x float> %a, %x
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fma_nxv8f16_x(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fma_nxv8f16_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #32768 // =0x8000
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: fmul z1.h, z1.h, z2.h
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.h, w8
+; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
+; CHECK-NEXT: fadd z0.h, z1.h, z0.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %m = fmul fast <vscale x 8 x half> %y, %z
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %m, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH8000, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fadd fast <vscale x 8 x half> %a, %x
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fma_nxv2f64_x(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fma_nxv2f64_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: fmul z1.d, z1.d, z2.d
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.d, x8
+; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
+; CHECK-NEXT: fadd z0.d, z1.d, z0.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %m = fmul fast <vscale x 2 x double> %y, %z
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %m, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double -0.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fadd fast <vscale x 2 x double> %a, %x
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 2 x i64> @add_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: add_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: add z1.d, p0/m, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer
+ %b = add <vscale x 2 x i64> %a, %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: add_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: add z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer
+ %b = add <vscale x 4 x i32> %a, %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @add_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: add_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: add z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer
+ %b = add <vscale x 8 x i16> %a, %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @add_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: add_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: add z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer
+ %b = add <vscale x 16 x i8> %a, %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @sub_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: sub_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: sub z0.d, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = sub <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @sub_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: sub_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sub z0.s, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = sub <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @sub_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: sub_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sub z0.h, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = sub <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @sub_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: sub_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: sub z0.b, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = sub <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mul_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mul_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #1 // =0x1
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: mul z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = mul <vscale x 2 x i64> %a, %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mul_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mul_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #1 // =0x1
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: mul z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = mul <vscale x 4 x i32> %a, %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mul_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mul_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #1 // =0x1
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: mul z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = mul <vscale x 8 x i16> %a, %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mul_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mul_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #1 // =0x1
+; CHECK-NEXT: sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT: mul z0.b, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %b = mul <vscale x 16 x i8> %a, %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @and_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: and_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = and <vscale x 2 x i64> %a, %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @and_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: and_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = and <vscale x 4 x i32> %a, %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @and_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: and_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = and <vscale x 8 x i16> %a, %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @and_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: and_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT: and z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
+ %b = and <vscale x 16 x i8> %a, %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @or_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: or_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer
+ %b = or <vscale x 2 x i64> %a, %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @or_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: or_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer
+ %b = or <vscale x 4 x i32> %a, %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @or_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: or_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer
+ %b = or <vscale x 8 x i16> %a, %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @or_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: or_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT: orr z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer
+ %b = or <vscale x 16 x i8> %a, %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @xor_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: xor_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z2.d, #0
+; CHECK-NEXT: mov z2.d, #0 // =0x0
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %x, <vscale x 2 x i64> zeroinitializer
+ %b = xor <vscale x 2 x i64> %a, %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @xor_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: xor_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #0 // =0x0
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> zeroinitializer
+ %b = xor <vscale x 4 x i32> %a, %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @xor_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: xor_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z2.h, #0
+; CHECK-NEXT: mov z2.h, #0 // =0x0
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %x, <vscale x 8 x i16> zeroinitializer
+ %b = xor <vscale x 8 x i16> %a, %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @xor_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: xor_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z2.b, #0
+; CHECK-NEXT: mov z2.b, #0 // =0x0
+; CHECK-NEXT: sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT: eor z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %x, <vscale x 16 x i8> zeroinitializer
+ %b = xor <vscale x 16 x i8> %a, %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @shl_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: shl_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = shl <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @shl_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: shl_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = shl <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @shl_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: shl_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = shl <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @shl_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: shl_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = shl <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @ashr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: ashr_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = ashr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @ashr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: ashr_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = ashr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @ashr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: ashr_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = ashr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @ashr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: ashr_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = ashr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @lshr_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: lshr_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z2.d, #0
+; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %a = lshr <vscale x 2 x i64> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @lshr_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: lshr_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = lshr <vscale x 4 x i32> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @lshr_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: lshr_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
+; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %a = lshr <vscale x 8 x i16> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @lshr_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: lshr_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
+; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %a = lshr <vscale x 16 x i8> %x, %y
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mla_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mla_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %y, %z
+ %a = add <vscale x 2 x i64> %m, %x
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mla_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mla_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %y, %z
+ %a = add <vscale x 4 x i32> %m, %x
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mla_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mla_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %y, %z
+ %a = add <vscale x 8 x i16> %m, %x
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mla_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mla_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %y, %z
+ %a = add <vscale x 16 x i8> %m, %x
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 2 x i64> @mls_nxv2i64_y(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i64> %z, <vscale x 2 x i64> %n) {
+; CHECK-LABEL: mls_nxv2i64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z3.d, #0
+; CHECK-NEXT: msb z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 2 x i64> %n, zeroinitializer
+ %m = mul <vscale x 2 x i64> %x, %y
+ %a = sub <vscale x 2 x i64> %z, %m
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %y
+ ret <vscale x 2 x i64> %b
+}
+
+define <vscale x 4 x i32> @mls_nxv4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %z, <vscale x 4 x i32> %n) {
+; CHECK-LABEL: mls_nxv4i32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z3.s, #0
+; CHECK-NEXT: msb z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %m = mul <vscale x 4 x i32> %x, %y
+ %a = sub <vscale x 4 x i32> %z, %m
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
+ ret <vscale x 4 x i32> %b
+}
+
+define <vscale x 8 x i16> @mls_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %z, <vscale x 8 x i16> %n) {
+; CHECK-LABEL: mls_nxv8i16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z3.h, #0
+; CHECK-NEXT: msb z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 8 x i16> %n, zeroinitializer
+ %m = mul <vscale x 8 x i16> %x, %y
+ %a = sub <vscale x 8 x i16> %z, %m
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
+ ret <vscale x 8 x i16> %b
+}
+
+define <vscale x 16 x i8> @mls_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z, <vscale x 16 x i8> %n) {
+; CHECK-LABEL: mls_nxv16i8_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z3.b, #0
+; CHECK-NEXT: msb z0.b, p0/m, z1.b, z2.b
+; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 16 x i8> %n, zeroinitializer
+ %m = mul <vscale x 16 x i8> %x, %y
+ %a = sub <vscale x 16 x i8> %z, %m
+ %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
+ ret <vscale x 16 x i8> %b
+}
+
+define <vscale x 4 x float> @fadd_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fadd_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.s, w8
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: fadd z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %x, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float -0.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fadd <vscale x 4 x float> %a, %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fadd_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fadd_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #32768 // =0x8000
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.h, w8
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: fadd z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %x, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH8000, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fadd <vscale x 8 x half> %a, %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fadd_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fadd_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: mov z2.d, x8
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: fadd z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %x, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double -0.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fadd <vscale x 2 x double> %a, %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fsub_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fsub_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsub z0.s, z0.s, z1.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fsub <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fsub_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fsub_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fsub z0.h, z0.h, z1.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fsub <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fsub_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fsub_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsub z0.d, z0.d, z1.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fsub <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmul_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmul_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fmov z2.s, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT: fmul z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x float> %x, <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 1.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+ %b = fmul <vscale x 4 x float> %a, %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmul_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmul_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fmov z2.h, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT: fmul z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = select <vscale x 8 x i1> %c, <vscale x 8 x half> %x, <vscale x 8 x half> shufflevector (<vscale x 8 x half> insertelement (<vscale x 8 x half> poison, half 0xH3C00, i64 0), <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer)
+ %b = fmul <vscale x 8 x half> %a, %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmul_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmul_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fmov z2.d, #1.00000000
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
+; CHECK-NEXT: fmul z0.d, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = select <vscale x 2 x i1> %c, <vscale x 2 x double> %x, <vscale x 2 x double> shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 1.000000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+ %b = fmul <vscale x 2 x double> %a, %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fdiv_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fdiv_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z2.s, #0.0
+; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = fdiv <vscale x 4 x float> %x, %y
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fdiv_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fdiv_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z2.h, #0.0
+; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = fdiv <vscale x 8 x half> %x, %y
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fdiv_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fdiv_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z2.d, #0.0
+; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: not p1.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = fdiv <vscale x 2 x double> %x, %y
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fmai_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fmai_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %a = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %x)
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fmai_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fmai_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %a = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %x)
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fmai_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fmai_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %a = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %x)
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+define <vscale x 4 x float> @fma_nxv4f32_y(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z, <vscale x 4 x float> %n) {
+; CHECK-LABEL: fma_nxv4f32_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: fcmle p1.s, p0/z, z3.s, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 4 x float> %n, zeroinitializer
+ %m = fmul fast <vscale x 4 x float> %y, %z
+ %a = fadd fast <vscale x 4 x float> %m, %x
+ %b = select <vscale x 4 x i1> %c, <vscale x 4 x float> %a, <vscale x 4 x float> %y
+ ret <vscale x 4 x float> %b
+}
+
+define <vscale x 8 x half> @fma_nxv8f16_y(<vscale x 8 x half> %x, <vscale x 8 x half> %y, <vscale x 8 x half> %z, <vscale x 8 x half> %n) {
+; CHECK-LABEL: fma_nxv8f16_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT: fcmle p1.h, p0/z, z3.h, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 8 x half> %n, zeroinitializer
+ %m = fmul fast <vscale x 8 x half> %y, %z
+ %a = fadd fast <vscale x 8 x half> %m, %x
+ %b = select <vscale x 8 x i1> %c, <vscale x 8 x half> %a, <vscale x 8 x half> %y
+ ret <vscale x 8 x half> %b
+}
+
+define <vscale x 2 x double> @fma_nxv2f64_y(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z, <vscale x 2 x double> %n) {
+; CHECK-LABEL: fma_nxv2f64_y:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: fcmle p1.d, p0/z, z3.d, #0.0
+; CHECK-NEXT: not p0.b, p0/z, p1.b
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+entry:
+ %c = fcmp ugt <vscale x 2 x double> %n, zeroinitializer
+ %m = fmul fast <vscale x 2 x double> %y, %z
+ %a = fadd fast <vscale x 2 x double> %m, %x
+ %b = select <vscale x 2 x i1> %c, <vscale x 2 x double> %a, <vscale x 2 x double> %y
+ ret <vscale x 2 x double> %b
+}
+
+
+define <vscale x 4 x i32> @mul_nxv4i32_multiuse_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n, ptr %p) {
+; CHECK-LABEL: mul_nxv4i32_multiuse_x:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z2.s, #0
+; CHECK-NEXT: mov z2.s, #1 // =0x1
+; CHECK-NEXT: sel z1.s, p1, z1.s, z2.s
+; CHECK-NEXT: mul z0.s, z1.s, z0.s
+; CHECK-NEXT: st1w { z1.s }, p0, [x0]
+; CHECK-NEXT: ret
+entry:
+ %c = icmp sgt <vscale x 4 x i32> %n, zeroinitializer
+ %a = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %y, <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+ store <vscale x 4 x i32> %a, ptr %p
+ %b = mul <vscale x 4 x i32> %a, %x
+ ret <vscale x 4 x i32> %b
+}
+
+declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
+declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
More information about the llvm-commits
mailing list